A Survey of Low-voltage Low-Power Techniques and Challenges for CMOS Digital Circuits

Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivations and challenges of CMOS low-voltage low-power circuit are addressed. Various design methodologies are surveyed and summarized in whole. The paper attempts to quickly give readers a full-view conception in low-voltage low-power CMOS system design.

[1]  Angela Arapoyanni,et al.  Dynamic back bias CMOS driver for low-voltage applications , 2000 .

[2]  N. Ranganathan,et al.  LECTOR: a technique for leakage reduction in CMOS circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  M. Hamada,et al.  Low-power CMOS digital design with dual embedded adaptive power supplies , 2000, IEEE Journal of Solid-State Circuits.

[4]  Benton H. Calhoun,et al.  Flexible Circuits and Architectures for Ultralow Power , 2010, Proceedings of the IEEE.

[5]  K. Banerjee,et al.  Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits , 2009, IEEE Transactions on Electron Devices.

[6]  Yi-Jen Chan,et al.  A 0.5–7.5 GHz Ultra Low-Voltage Low-Power Mixer Using Bulk-Injection Method by 0.18- $\mu$m CMOS Technology , 2007, IEEE Microwave and Wireless Components Letters.

[7]  Sun-Young Hwang,et al.  Circuit partitioning algorithm for low-power design under area constraints using simulated annealing , 1999 .

[8]  L.S.Y. Wong,et al.  A very low-power CMOS mixed-signal IC for implantable pacemaker applications , 2004, IEEE Journal of Solid-State Circuits.

[9]  J. Liaw,et al.  Leakage scaling in deep submicron CMOS for SoC , 2002 .

[10]  Steven Trimberger,et al.  A 90-nm Low-Power FPGA for Battery-Powered Applications , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Yu-Cherng Hung,et al.  A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability , 2002 .

[12]  Gabriel A. Rincon-Mora,et al.  Designing 1-V op amps using standard digital CMOS technology , 1998 .

[13]  Vishwani D. Agrawal,et al.  Variable Input Delay CMOS Logic for Low Power Design , 2009, IEEE Trans. Very Large Scale Integr. Syst..

[14]  M. C. Chi,et al.  Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Axel Jantsch,et al.  Low-power and error protection coding for network-on-chip traffic , 2008, IET Comput. Digit. Tech..

[16]  Massoud Pedram,et al.  Low-power RT-level synthesis techniques: a tutorial , 2005 .

[17]  Jason Helge Anderson,et al.  Low-Power Programmable FPGA Routing Circuitry , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Shigeru Kawanaka,et al.  A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology , 2003, IEEE J. Solid State Circuits.

[19]  Jia Di,et al.  Teaching low-power electronic design in electrical and computer engineering , 2005, IEEE Transactions on Education.

[20]  Yuan-Sun Chu,et al.  A Low-Power Multiplier With the Spurious Power Suppression Technique , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Jeffrey A. Davis,et al.  Optimization of throughput performance for low-power VLSI interconnects , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Sorin A. Huss,et al.  Efficient algorithms for multilevel power estimation of VLSI circuits , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Malgorzata Marek-Sadowska,et al.  Low-power buffered clock tree design , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Kaushik Roy,et al.  Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Yu-Cherng Hung,et al.  1-V CMOS comparator for programmable analog rank-order extractor , 2003 .

[26]  Volkan Kursun,et al.  Low Power and High Speed Multi Threshold Voltage Interface Circuits , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[27]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[28]  Huailin Liao,et al.  0.5 V ultra-low power wideband LNA with forward body bias technique , 2009 .

[29]  K. Imai,et al.  Design Methodology of Body-Biasing Scheme for Low Power System LSI With Multi- $V_{\rm th}$ Transistors , 2007, IEEE Transactions on Electron Devices.

[30]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[31]  Hiroshi Kawaguchi,et al.  VTH-hopping scheme to reduce subthreshold leakage for low-power processors , 2002, IEEE J. Solid State Circuits.

[32]  Kaushik Roy,et al.  Vertically integrated SOI circuits for low-power and high-performance applications , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[33]  Tzuen-Hsi Huang,et al.  Back-gate forward bias method for low-voltage CMOS digital circuits , 1996 .

[34]  Li Shang,et al.  Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[35]  Yu-Cherng Hung,et al.  A low-voltage wide-input CMOS comparator for sensor application using back-gate technique. , 2004, Biosensors & bioelectronics.

[36]  Mohammad Sharifkhani,et al.  Segmented Virtual Ground Architecture for Low-Power Embedded SRAM , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[37]  Sachin S. Sapatnekar,et al.  Low-power clock distribution using multiple voltages and reduced swings , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[38]  L.T. Clark,et al.  An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage , 2006, IEEE Journal of Solid-State Circuits.

[39]  Rongtian Zhang,et al.  Low-power high-performance double-gate fully depleted SOI circuit design , 2002 .

[40]  Mohamed I. Elmasry,et al.  Circuit techniques for CMOS low-power high-performance multipliers , 1996 .

[41]  Yih Wang,et al.  Low-Power SRAMs in Nanoscale CMOS Technologies , 2008, IEEE Transactions on Electron Devices.