Compact Test Generation Using a Frozen Clock Testing Strategy

Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach to generating compact test sequences for sequential circuits. Our approach combines a conventional ATPG algorithm, a technique based on the frozen clock testing strategy, and a dynamic compaction method based on a genetic algorithm. The frozen clock strategy temporarily suspends the sequential behavior of the circuit by stopping its clock and applying several vectors to increase the number of faults detected without changing the circuit state. Results show that test sets generated using the new approach are more compact than those generated by previous approaches for many circuits.

[1]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[2]  Kewal K. Saluja,et al.  Methods for dynamic test vector compaction in sequential test generation , 1996, Proceedings of 9th International Conference on VLSI Design.

[3]  Janak H. Patel,et al.  PROOFS: a fast, memory efficient sequential circuit fault simulator , 1990, 27th ACM/IEEE Design Automation Conference.

[4]  D. E. Goldberg,et al.  Genetic Algorithms in Search , 1989 .

[5]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[6]  Yanti Irene Santoso.  Compact Test Generation Based on a Frozen Clock Testing Strategy , 1999 .

[7]  Elizabeth M. Rudnick,et al.  Efficient Techniques for Dynamic Test Sequence Compaction , 1999, IEEE Trans. Computers.

[8]  Irith Pomeranz,et al.  On generating compact test sequences for synchronous sequential circuits , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[9]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[10]  Elizabeth M. Rudnick,et al.  A genetic algorithm framework for test generation , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Elizabeth M. Rudnick,et al.  Putting the squeeze on test sequences , 1997, Proceedings International Test Conference 1997.

[12]  Irith Pomeranz,et al.  Dynamic test compaction for synchronous sequential circuits using static compaction techniques , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

[13]  Anand Raghunathan,et al.  Dynamic test sequence compaction for sequential circuits , 1996, Proceedings of 9th International Conference on VLSI Design.

[14]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[15]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[16]  Miron Abramovici,et al.  FREEZE: a new approach for testing sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.