Building compressed sensing systems : sensors and analog-to-information converters

Compressed sensing (CS) is a promising method for recovering sparse signals from fewer measurements than ordinarily used in the Shannon’s sampling theorem [14]. Introducing the CS theory has sparked interest in designing new hardware architectures which can be potential substitutions for traditional hardware architectures in communication systems. CS-based wireless sensors and analog-to-information converters (AIC) are two examples of CS-based systems. It has been claimed that such systems are potentially providing higher performance and lower power consumption compared to traditional systems. However, since there is no end-to-end hardware implementation of these systems, it is difficult to make a fair hardware-to-hardware comparison with other implemented systems. This project aims to fill this gap by examining the energy-performance design space for CS in the context of both practical wireless sensor and AIC. One of the limitations of CS-based systems is that they are employing iterative algorithms to recover the signal. Since these algorithms are slow, the hardware solution has become crucial for higher performance and speed. In this work, we also implement a suitable CS reconstruction algorithm in hardware. Thesis Supervisor: Vladimir Stojanović Title: Associate Professor