Design of reliable VLSI circuits using simulation techniques

An iterative simulation method of predicting the impact of progressive device degradation on circuit performance due to common microelectronic failure mechanisms is described. Simulation schemes for the lifetime prediction of ASICs as well as modeling requirements for accurate and efficient simulation are presented. These simulation schemes have been implemented in the prototype reliability simulator RELY to evaluate circuit performance degradation and provide reliability enhancement information. Hot-carrier effects on submicrometer digital and analog circuits are used to demonstrate the approach. Experimental results on precharging circuitry for sense amplifiers and operational amplifiers are presented. >

[1]  K. Seki,et al.  Circuit aging simulator (CAS) , 1988, Technical Digest., International Electron Devices Meeting.

[2]  Chenming Hu,et al.  Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.

[3]  Tetsuya Iizuka,et al.  Hot-carrier generation in submicrometer VLSI environment , 1986 .

[4]  Kwyro Lee,et al.  A new CMOS NAND logic circuit for reducing hot-carrier problems , 1989 .

[5]  Swei-Yam Yu,et al.  Substrate Current Modeling for Circuit Simulation , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Bing J. Sheu,et al.  BSIM: Berkeley short-channel IGFET model for MOS transistors , 1987 .

[7]  Ibrahim N. Hajj,et al.  Electromigration median time-to-failure based on a stochastic current waveform , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[8]  Bing J. Sheu,et al.  An integrated-circuit reliability simulator-RELY , 1989 .

[9]  M. Bloom,et al.  Mixed-Mode Simulation , 1990 .