A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband

A 250 MHz analog baseband chain for ultra-wideband was implemented in a 1.2 V 0.13 ¿ m CMOS process. The chip has an active area of 0.8 mm2. In the analog baseband, PGAs and filters are carried out by current-mode amplifiers to achieve wide bandwidth and wide dynamic range of gain, as well as low noise and high linearity. Besides, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers. A 6 th-order Chebyshev low-pass filter realized in Gm-C topology is designed in the baseband chain for channel selection. Digitally-assisted DC-offset calibration improves second-order distortion of the entire chain. The design achieves a maximum gain of 73 dB and a dynamic range of 82 dB. Measured noise figure is 14 dB, an IIP3 of -6 dBV, and IIP2 of -5 dBV at the maximum gain mode. The analog baseband chain consumes 56.4 mA under supply of 1.2 V.

[1]  Fei Yuan,et al.  CMOS Current-Mode Circuits for Data Communications (Analog Circuits and Signal Processing) , 2006 .

[2]  Saska Lindfors,et al.  A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  D.M.W. Leenaerts,et al.  An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology , 2005, IEEE Journal of Solid-State Circuits.

[4]  G.S. Sahota,et al.  High dynamic range variable-gain amplifier for CDMA wireless applications , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[5]  J.J.F. Rijns CMOS Low-Distortion High-Frequency Variable-Gain Amplifier , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[6]  A.A. Abidi,et al.  A 3.1- to 8.2-GHz zero-IF receiver and direct frequency synthesizer in 0.18-/spl mu/m SiGe BiCMOS for mode-2 MB-OFDM UWB communication , 2005, IEEE Journal of Solid-State Circuits.

[7]  Erik Bruun,et al.  Bandwidth optimization of a low power, high speed CMOS current op amp , 1995 .

[8]  Gordon W. Roberts,et al.  A general class of current amplifier-based biquadratic filter circuits , 1992 .

[9]  Andrea Baschirotto,et al.  A CMOS 5 nV$/\surd $Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN , 2008, IEEE Journal of Solid-State Circuits.

[10]  S.S. Taylor,et al.  A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[11]  Kenneth C. Smith,et al.  The current conveyor—A new circuit building block , 1968 .

[12]  R. Weigel,et al.  Digital Adaptive IIP2 Calibration Scheme for CMOS Downconversion Mixers , 2008, IEEE Journal of Solid-State Circuits.

[13]  Chien-Nan Kuo,et al.  A 1.2V interference-sturdiness, DC-offset calibrated CMOS receiver utilizing a current-mode filter for UWB , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[14]  Gordon W. Roberts,et al.  All current-mode frequency selective circuits , 1989 .

[15]  M. E. Valkenburg,et al.  Design of Analog Filters , 2001 .

[16]  L.E. Larson,et al.  A Low-Cost and Low-Power CMOS Receiver Front-End for MB-OFDM Ultra-Wideband Systems , 2007, IEEE Journal of Solid-State Circuits.

[17]  Gaetano Palumbo,et al.  CMOS current amplifiers , 1999 .

[18]  Shen-Iuan Liu,et al.  40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[19]  A. A. Abidi,et al.  General relations between IP2, IP3, and offsets in differential circuits and the effects of feedback , 2003 .

[20]  Peng-Un Su A 0.25-/spl mu/m CMOS OPLL transmitter IC for GSM and DCS applications , 2005, IEEE Transactions on Microwave Theory and Techniques.

[21]  David J. Allstot,et al.  A high gain current-mode operational amplifier , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.