Filter Bank Multi Carrier (FBMC), Generalized Frequency Division Multiplexing (GFDM), Universal Filtered Multi-Carrier (UFMC), and Filtered-Orthogonal Frequency Division Multiplexing (f-OFDM) techniques are proposed for their suitability to 5G requirements. On one side f-OFDM show very good out of band emission characteristic as well as it promises flexibility requirement of 5G. For enhanced Mobile Broad Band (eMBB), it provides a natural extension to simple OFDM. In addition to the acceptable performance achieved through applying f-OFDM, study of hardware cost associated with its implementation is very important which is missing in previous research work. FIR filtering is a key processing block in f-OFDM and differentiates it from its predecessor OFDM waveform. Hence, this paper is aimed at real time hardware implementation of a flexible hardware architecture related to filtering part of Filtered-OFDM transmitter. In this regard, two flexible solutions for f-OFDM FIR filter are presented. These both schemes are modelled in Verilog HDL, which are then synthesized and implemented on Virtex-7 FPGA. Finally, a comparison of these solutions is also provided. Both models provide the flexible novelty solutions for FIR filtering of f-OFDM waveform as well as these architectures shows an outstanding 5 times decrement in hardware utilization in terms of adders and multipliers as compared to previous filtering technique used in UFMC.