From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits

It is a widely supported prediction that conventional computer hardware technologies are going to reach their limits in the near future. Consequently, researchers are working on alternatives. Reversible circuits are one promising direction with applications e.g. in low-power design or quantum computation. However, no real design flow for this new kind of circuits exists so far. In this paper, the progress in the development of design methods for reversible circuits is reviewed -- with a particular focus on the synthesis steps. After a brief review on reversible circuits, the general idea of common synthesis approaches is described. This includes methods based on truth table descriptions, methods applicable to larger functions, and finally an approach based on a programming language. Discussions and an outlook to future work conclude this paper.

[1]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[2]  Tommaso Toffoli,et al.  Reversible Computing , 1980, ICALP.

[3]  T. Toffoli,et al.  Conservative logic , 2002, Collision-Based Computing.

[4]  R Cuykendall,et al.  Reversible optical computing circuits. , 1987, Optics letters.

[5]  R. Merkle Reversible electronic logic using switches , 1993 .

[6]  Peter W. Shor,et al.  Algorithms for quantum computation: discrete logarithms and factoring , 1994, Proceedings 35th Annual Symposium on Foundations of Computer Science.

[7]  Barenco,et al.  Elementary gates for quantum computation. , 1995, Physical review. A, Atomic, molecular, and optical physics.

[8]  Ruby B. Lee,et al.  Bit permutation instructions for accelerating software cryptography , 2000, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors.

[9]  R. Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[10]  Ruby B. Lee,et al.  Architectural enhancements for fast subword permutations with repetitions in cryptographic applications , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[11]  I. Chuang,et al.  Experimental realization of Shor's quantum factoring algorithm using nuclear magnetic resonance , 2001, Nature.

[12]  Alexis De Vos,et al.  A reversible carry-look-ahead adder using control gates , 2002, Integr..

[13]  John P. Hayes,et al.  Synthesis of reversible logic circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Gerhard W. Dueck,et al.  A transformation based algorithm for reversible logic synthesis , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[15]  J. Hayes,et al.  Fault testing for reversible circuits , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[16]  Gerhard W. Dueck,et al.  Reversible cascades with minimal garbage , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Pawel Kerntopf,et al.  A new heuristic algorithm for reversible logic synthesis , 2004, Proceedings. 41st Design Automation Conference, 2004..

[18]  Yasuhiro Takahashi,et al.  A linear-size quantum circuit for addition with no ancillary qubits , 2005, Quantum Inf. Comput..

[19]  M. B. Srinivas,et al.  The need of DNA computing: reversible designs of adders and multipliers using Fredkin gate , 2005, International Symposium on Optomechatronic Technologies.

[20]  H. Thapliyal,et al.  A beginning in the reversible logic synthesis of sequential circuits , 2005 .

[21]  John P. Hayes,et al.  A Family of Logical Fault Models for Reversible Circuits , 2005, 14th Asian Test Symposium (ATS'05).

[22]  Martin Lukac,et al.  Test generation and fault localization for quantum circuits , 2005, 35th International Symposium on Multiple-Valued Logic (ISMVL'05).

[23]  Gerhard W. Dueck,et al.  Toffoli network synthesis with templates , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  Niraj K. Jha,et al.  An Algorithm for Synthesis of Reversible Logic Circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  Guowu Yang,et al.  Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  John P. Hayes,et al.  Checking equivalence of quantum circuits and states , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[27]  Thierry Paul,et al.  Quantum computation and quantum information , 2007, Mathematical Structures in Computer Science.

[28]  M. Thornton,et al.  ESOP-based Toffoli Gate Cascade Generation , 2007, 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

[29]  Chun-Yao Wang,et al.  Synthesis of Reversible Sequential Elements , 2007 .

[30]  Robert Glück,et al.  A reversible programming language and its invertible self-interpreter , 2007, PEPM '07.

[31]  Gerhard W. Dueck,et al.  Techniques for the synthesis of reversible Toffoli networks , 2006, TODE.

[32]  Robert Wille,et al.  RevLib: An Online Resource for Reversible Functions and Reversible Circuits , 2008, 38th International Symposium on Multiple Valued Logic (ismvl 2008).

[33]  Mozammel H. A. Khan,et al.  Cost Reduction in Nearest Neighbour Based Synthesis of Quantum Boolean Circuits , 2008, Eng. Lett..

[34]  Robert Glück,et al.  Optimized reversible binary-coded decimal adders , 2008, J. Syst. Archit..

[35]  Sy-Yen Kuo,et al.  An XQDD-Based Verification Method for Quantum Circuits , 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[36]  Robert Wille,et al.  Synthesizing Reversible Circuits for Irreversible Functions , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[37]  Robert Wille,et al.  Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[38]  Hafiz Md. Hasan Babu,et al.  Efficient Design of Shift Registers Using Reversible Logic , 2009, 2009 International Conference on Signal Processing Systems.

[39]  Robert Wille,et al.  Reversible Logic Synthesis with Output Permutation , 2009, 2009 22nd International Conference on VLSI Design.

[40]  Stefan Frehse,et al.  Debugging of Toffoli networks , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[41]  Robert Wille,et al.  Equivalence Checking of Reversible Circuits , 2009, 2009 39th International Symposium on Multiple-Valued Logic.

[42]  Robert Wille,et al.  Towards a Design Flow for Reversible Logic , 2010 .

[43]  Robert Wille,et al.  BDD-based synthesis of reversible logic for large functions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[44]  N. Ranganathan,et al.  Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs , 2010, JETC.

[45]  Robert Wille,et al.  Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition , 2010, 2010 5th International Design and Test Workshop.

[46]  Robert Wille,et al.  SyReC: A Programming Language for Synthesis of Reversible Circuits , 2010, FDL.

[47]  Morteza Saheb Zamani,et al.  Reversible circuit synthesis using a cycle-based approach , 2010, JETC.

[48]  ESOP-Based Toffoli Network Generation with Transformations , 2010, 2010 40th IEEE International Symposium on Multiple-Valued Logic.

[49]  Robert Wille,et al.  SAT-based ATPG for reversible circuits , 2010, 2010 5th International Design and Test Workshop.

[50]  Robert Wille,et al.  Reducing the number of lines in reversible circuits , 2010, Design Automation Conference.

[51]  Robert Wille,et al.  Synthesizing multiplier in reversible logic , 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[52]  Robert Wille,et al.  Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic , 2010, RC@ETAPS.

[53]  Robert Wille,et al.  Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates , 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

[54]  Robert Wille,et al.  Synthesis of quantum circuits for linear nearest neighbor architectures , 2011, Quantum Inf. Process..

[55]  Robert Wille,et al.  Determining the minimal number of lines for large reversible circuits , 2011, 2011 Design, Automation & Test in Europe.

[56]  Stefan Frehse,et al.  RevKit: A Toolkit for Reversible Circuit Design , 2012, J. Multiple Valued Log. Soft Comput..

[57]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .