A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach

In this paper, we present a new approach for the one-dimensional gate assignment problem. The original minimization problem is transformed into a restricted problem, and then a new heuristic algorithm is applied to it. The solution obtained by the algorithm is interpreted as a solution for the original problem. The whole process of the approach has been implemented and tested with various examples. Experimental results show that our approach can approximately produce optimum solutions.

[1]  Rui Wang,et al.  Gate Matrix Layout , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  A.D. Lopez,et al.  A dense gate matrix layout method for MOS VLSI , 1980, IEEE Transactions on Electron Devices.

[3]  E. Kuh,et al.  One-dimensional logic gate assignment and interval graphs , 1979, COMPSAC.

[4]  A. Weinberger Large Scale Integration of MOS Complex Logic: A Layout Method , 1967 .

[5]  K. Kani,et al.  A heuristic procedure for ordering MOS arrays , 1975, DAC '75.