Compensating for variability in FPGAs by re-mapping and re-placement

Two complementary techniques for reducing the effect of within-die variability on the critical path delay in FPGA circuits are reported. The first technique selects the best LUT mapping from a set of alternative mappings of a logic function for each LUT cluster in the FPGA. The second selects the best assignment of LUTs to physical locations within a cluster. The techniques can be used together, and are shown in Monte Carlo experiments to reduce both the mean and standard deviation of critical path delay.

[1]  David Blaauw,et al.  Statistical Analysis and Optimization for VLSI: Timing and Power , 2005, Series on Integrated Circuits and Systems.

[2]  Peter Y. K. Cheung,et al.  Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis , 2007, FPGA '07.

[3]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[4]  Peter Y. K. Cheung,et al.  Within-die delay variability in 90nm FPGAs and beyond , 2006, 2006 IEEE International Conference on Field Programmable Technology.

[5]  Jason Cong,et al.  DAG-Map: graph-based FPGA technology mapping for delay optimization , 1992, IEEE Design & Test of Computers.

[6]  Peter Y. K. Cheung,et al.  Characterisation of FPGA Clock Variability , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[7]  Jinjun Xiong,et al.  FPGA Performance Optimization Via Chipwise Placement Considering Process Variations , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[8]  Kazutoshi Kobayashi,et al.  A yield and speed enhancement scheme under within-die variations on 90nm LUT array , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[9]  Sani R. Nassif.  Design for Variability in DSM Technologies , 2000 .

[10]  A. Asenov,et al.  Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .

[11]  Hanpei Koike,et al.  Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations , 2008, TRETS.