An Analysis of Loop Permutation on the HP PA-RISC

In modern computers, processor speed has become significantly faster than memory speed. Cache memories are designed to overcome this difference, but they are only effective when programs exhibit data locality. In this report, we present an experiment with compiler optimizations to improve data locality based on a simple cost model [14]. The model computes both temporal and spatial reuse of cache lines to find desirable loop permutations. The cost model drives the application of compound transformations consisting of loop permutation, loop distribution, and loop reversal.

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