Bilayer Graphene Tunneling FET for Sub-0.2 V Digital CMOS Logic Applications
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Marian Verhelst | Iuliana Radu | Aaron Thean | Praveen Raghavan | Marc Heyns | Stefan De Gendt | Tarun K. Agarwal | A. Thean | I. Radu | M. Verhelst | M. Heyns | P. Raghavan | S. De Gendt | T. Agarwal | A. Nourbakhsh | Amirhasan Nourbakhsh
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