Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)

A multilevel interconnect architecture design methodology that optimizes the interconnect cross-sectional dimensions of each metal layer is introduced that reduces logic macrocell area, cycle time, power consumption or number of metal layers. The predictive capability of this methodology, which is based on a stochastic wiring distribution, provides insight into defining the process technology parameters for current and future generations of microprocessors and application-specific integrated circuits (ASICs). Using this methodology on an ASIC logic macrocell case study for the 100 nm technology generation, the optimized n-tier multilevel interconnect architecture reduces macrocell area by 32%, cycle time by 16% or number of wiring tracks required on the topmost tier by 62% compared to a conventional design where pitches are doubled for every successive pair of levels. A new repeater insertion methodology is also described that further enhances gigascale integration (GSI) system performance. By using repeaters, a further reduction of 70% in macrocell area, 18% in cycle time, 25% in number of metal levels or 44% in power dissipation is achieved, when compared to an n-tier design without repeaters. The key distinguishing feature of the methodology is its comprehensive framework that simultaneously solves two distinct problems-optimal wire sizing and wiring layer assignment-using independent constraints on maximum repeater area for efficient design space exploration to optimize the area, power, frequency, and metal levels of a GSI logic megacell.

[1]  W. Donath.  Wire length distribution for placements of computer logic , 1981 .

[2]  James D. Meindl,et al.  Performance enhancement through optimal n-tier multilevel interconnect architectures , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[3]  Andrew B. Kahng,et al.  Requirements for models of achievable routing , 2000, ISPD '00.

[4]  James D. Meindl,et al.  A physical alpha-power law MOSFET model , 1999 .

[5]  Takayasu Sakurai,et al.  Delay analysis of series-connected MOSFET circuits , 1991 .

[6]  James D. Meindl,et al.  Optimal repeater insertion for n-tier multilevel interconnect architectures , 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

[7]  H. Wong,et al.  CMOS scaling into the nanometer regime , 1997, Proc. IEEE.

[8]  Andrew B. Kahng,et al.  Wiring layer assignments with consistent stage delays , 2000, SLIP '00.

[9]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[10]  Keith A. Bowman,et al.  Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[11]  Qiang Chen,et al.  A compact physical via blockage model , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[12]  James D. Meindl,et al.  A generic system simulator with novel on-chip cache and throughput models for gigascale integration , 1998 .

[13]  M. Hussein,et al.  A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[14]  J.D. Meindl,et al.  Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.

[15]  G. A. Sai-Halasz,et al.  Performance trends in high-end processors , 1995, Proc. IEEE.

[16]  James D. Meindl,et al.  Low power microelectronics: retrospect and prospect , 1995, Proc. IEEE.

[17]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[18]  Bulent Basaran,et al.  Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor , 2000, ISPD '00.

[19]  Takayasu Sakurai,et al.  Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .