An optimized topology reconfiguration bidirectional searching fault-tolerant algorithm for REmesh network-on-chip

This paper shows an optimized topology reconfiguration algorithm by using bidirectional searching method to tolerate faulty cores in REmesh (reconfigurable 2D mesh) Network-on-Chip architecture. Compared with traditional algorithm, the proposed algorithm has a higher fault-tolerate capability and performs better in the finding out reconfiguration solution. Simulation results show that 93.85% successful reconfiguration rate can be guaranteed when less than 10.71% of the total cores are faulty. In the 7×8 network, when the faulty cores reach 7, successful reconfiguration rate is 65.9% with the proposed algorithm, which enhanced 14% compared with TRARE algorithm.

[1]  D. Geer,et al.  Chip makers turn to multicore processors , 2005, Computer.

[2]  Radu Marculescu,et al.  FARM: Fault-aware resource management in NoC-based multiprocessor platforms , 2011, 2011 Design, Automation & Test in Europe.

[3]  Doug Burger,et al.  Exploiting microarchitectural redundancy for defect tolerance , 2003, Proceedings 21st International Conference on Computer Design.

[4]  Shekhar Borkar Thousand Core ChipsA Technology Perspective , 2007, DAC 2007.

[5]  Axel Jantsch,et al.  Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Jin-Xiang Wang,et al.  Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm , 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.