论文信息 - Implementation of the block cipher Rijndael using Altera FPGA

Implementation of the block cipher Rijndael using Altera FPGA

A short description of the block cipher Rijndael is presented. Hardware implementation by means of the FPGA (field programmable gate array) technology is evaluated. Implementation results compared with other hardware implementations are summarized.

P. Mroczkowski

[1] Elaine B. Barker,et al. Status Report on the First Round of the Development of the Advanced Encryption Standard , 1999, Journal of Research of the National Institute of Standards and Technology.

[2] Joan Daemen,et al. AES Proposal : Rijndael , 1998 .

[3] Viktor Fischer. Realization of the Round 2 AES Candidates using Altera FPGA , 2000 .