Folklore Confirmed: Compiling for Speed = Compiling for Energy

As we move towards exa-scale computing, energy is becoming increasingly important, even in the high performance computing arena. However, the simple equation, Energy = Power \(\times \) Time, suggests that optimizing for speed already optimizes for energy, under the assumption that Power is constant. When power is not constant, a strategy that achieves energy savings at the cost of slower execution is Dynamic Voltage and Frequency Scaling (DVFS). However, DVFS is currently applicable only to the processor, and the entire system has many other sources of power dissipation. We show that there is little to gain in compilers by trying to trade off speed for energy using DVFS. It is best to produce code that runs full-throttle, completing as quickly as possible, an approach called “race to sleep.” Our result is based on analyses of a high-level energy model that characterizes energy consumption, related to survey of power consumption trends of recent processors for both desktop and server, as well as Cray supercomputers.

[1]  Vibhore Vardhan,et al.  Power Consumption Breakdown on a Modern Laptop , 2004, PACS.

[2]  David E. Culler,et al.  Power Optimization - a Reality Check , 2009 .

[3]  Klaus-Dieter Lange,et al.  ASSESSING TRENDS OVER TIME IN PERFORMANCE , COSTS , AND ENERGY USE FOR SERVERS , 2009 .

[4]  Rami G. Melhem,et al.  Corollaries to Amdahl's Law for Energy , 2008, IEEE Computer Architecture Letters.

[5]  David K. Lowenthal,et al.  Just In Time Dynamic Voltage Scaling: Exploiting Inter-Node Slack to Save Energy in MPI Programs , 2005, ACM/IEEE SC 2005 Conference (SC'05).

[6]  Wu-chun Feng,et al.  Understanding Power Measurement Implications in the Green500 List , 2010, 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing.

[7]  Mahmut T. Kandemir,et al.  Compiler-directed high-level energy estimation and optimization , 2005, TECS.

[8]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[9]  Ulrich Kremer,et al.  The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction , 2003, PLDI '03.

[10]  Wolf-Dietrich Weber,et al.  Power provisioning for a warehouse-sized computer , 2007, ISCA '07.

[11]  Dong Li,et al.  PowerPack: Energy Profiling and Analysis of High-Performance Systems and Applications , 2010, IEEE Transactions on Parallel and Distributed Systems.

[12]  Mahmut T. Kandemir,et al.  Reducing power with performance constraints for parallel sparse applications , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[13]  Mahmut T. Kandemir,et al.  Energy optimization techniques in cluster interconnects , 2003, ISLPED '03.

[14]  Anantha Chandrakasan,et al.  JouleTrack: a web based tool for software energy profiling , 2001, DAC '01.

[15]  Ricardo Bianchini,et al.  Application transformations for energy and performance-aware device management , 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.

[16]  Chris Fallin,et al.  Memory power management via dynamic voltage/frequency scaling , 2011, ICAC '11.

[17]  Rami G. Melhem,et al.  On the Interplay of Parallelization, Program Performance, and Energy Consumption , 2010, IEEE Transactions on Parallel and Distributed Systems.

[18]  Gernot Heiser,et al.  Dynamic voltage and frequency scaling: the laws of diminishing returns , 2010 .

[19]  Mahmut T. Kandemir,et al.  Compiler-directed voltage scaling on communication links for reducing power consumption , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[20]  Lizy Kurian John,et al.  Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events , 2007, 2007 IEEE International Symposium on Performance Analysis of Systems & Software.

[21]  Randy H. Katz,et al.  An energy case for hybrid datacenters , 2010, OPSR.

[22]  Kanad Ghose,et al.  Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization , 2004, PACS.

[23]  Thomas F. Wenisch,et al.  PowerNap: eliminating server idle power , 2009, ASPLOS.

[24]  Wu-chun Feng,et al.  A Power-Aware Run-Time System for High-Performance Computing , 2005, ACM/IEEE SC 2005 Conference (SC'05).

[25]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[26]  Vivek Tiwari,et al.  Reducing power in high-performance microprocessors , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[27]  Dean M. Tullsen,et al.  The effect of compiler optimizations on Pentium 4 power consumption , 2003, Seventh Workshop on Interaction Between Compilers and Computer Architectures, 2003. INTERACT-7 2003. Proceedings..