A parallel-in-time method for the transient simulation of SOI devices with drain current overshoots

This paper presents a new parallel-in-time algorithm for the two dimensional transient simulation of SOI devices. With this approach, simulation in both space and time domains is performed in parallel As a result, the CPU time is reduced significantly from the conventional serial-in-time method. This new approach fully exploits the inherent parallelism of the finite difference formulation of the basic semiconductor device equations and the massively parallel architecture of SIMD computers. The space domain computations are inherently parallel due to the nature of our technique of solving the finite-difference equations. Time domain parallelism is achieved by shifting the potentials from previous time points to subsequent points one-step forward along the time axis with each Gummel iteration. This algorithm employs a fixed-point iteration technique, therefore a direct solution of matrix equations is avoided. The algorithm is especially suitable for the transient simulation of SOI devices that exhibit transient drain current overshoot. Numerical experiments show that the new parallel-in-time method is up to eight times faster than the conventional serial-in-time method in SOI transient simulations. The program is coded in CM Fortran for the Connection Machine. >

[1]  Isaak D. Mayergoyz,et al.  A globally convergent algorithm for the solution of the steady‐state semiconductor device equations , 1990 .

[2]  Isaak D. Mayergoyz,et al.  Solution of the nonlinear Poisson equation of semiconductor device theory , 1986 .

[3]  Prithviraj Banerjee,et al.  A portable parallel algorithm for VLSI circuit extraction , 1993, [1993] Proceedings Seventh International Parallel Processing Symposium.

[4]  An efficient method to compute the maximum transient drain current overshoot in silicon on insulator devices , 1993 .

[5]  Yoshiyasu Takefuji,et al.  A parallel algorithm for channel routing problems [VLSI] , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Thomas I. Seidman,et al.  Iterative scheme for computer simulation of semiconductor devices , 1972 .

[7]  Resve A. Saleh,et al.  Parallel waveform-Newton algorithms for circuit simulation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  H. Tango,et al.  Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film , 1989 .

[9]  M. Gaitan,et al.  Investigation of the threshold voltage of MOSFETs with position- and potential-dependent interface trap distributions using a fixed-point iteration method , 1990 .

[10]  Ping Yang,et al.  Direct circuit simulation algorithms for parallel processing [VLSI] , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  K. Kato,et al.  Numerical analysis of switching characteristics in SOI MOSFET's , 1986, IEEE Transactions on Electron Devices.

[12]  Isaak D. Mayergoyz,et al.  Parallel Algorithm for the Solution of Nonlinear Poisson Equation of Semiconductor Device Theory and Its Implementation on the MPP , 1990, J. Parallel Distributed Comput..

[13]  Robert F. Lucas,et al.  A Parallel Solution Method for Large Sparse Systems of Equations , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Kenji Natori,et al.  Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFETs , 1990 .

[15]  Prithviraj Banerjee,et al.  Parallel algorithms for VLSI circuit extraction , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  H. Gummel,et al.  Large-signal analysis of a silicon Read diode oscillator , 1969 .

[17]  Alberto L. Sangiovanni-Vincentelli,et al.  A massively parallel algorithm for three-dimensional device simulation , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  P. Wild ON THE STABILITY OF TIME DISCRETISATIONS FOR THE SEMICONDUCTOR EQUATIONS , 1991 .

[19]  S. Odanaka,et al.  A mobility model for submicrometer MOSFET simulations including hot-carrier-induced device degradation , 1988 .

[20]  Donald J. Rose,et al.  A parallel block iterative method for the hydrodynamic device model , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  J.G. Fossum,et al.  Transient drain current and propagation delay in SOI CMOS , 1984, IEEE Transactions on Electron Devices.

[22]  Rob A. Rutenbar,et al.  Massively parallel switch-level simulation: a feasibility study , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..