Silicon-on-Nothing (SON)-an innovative process for advanced CMOS
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M. Jurczak | T. Skotnicki | M. Paoli | B. Tormen | J. Martins | J. Regolini | D. Dutartre | P. Ribot | D. Lenoble | R. Pantel | S. Monfray
[1] J. Colinge. Subthreshold slope of thin-film SOI MOSFET's , 1986, IEEE Electron Device Letters.
[2] D. Hisamoto,et al. A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET , 1989, International Technical Digest on Electron Devices Meeting.
[3] J. Colinge,et al. Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.
[4] D. Hisamoto,et al. A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET , 1990, IEEE Electron Device Letters.
[5] J. Colinge. Silicon-on-Insulator Technology: Materials to VLSI , 1991 .
[6] Y. Omura,et al. 0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer , 1991 .
[7] J. Colinge. Silicon-on-Insulator Technology , 1991 .
[8] M. V. Fischetti,et al. Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.
[9] Y. Kiyota,et al. Ultra-thin-base Si bipolar transistor using rapid vapor-phase direct doping (RVD) , 1992 .
[10] K. F. Lee,et al. Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .
[11] H. Iwai,et al. A New Scaling Methodology For The 0.1 - 0.025/spl mu/m MOSFET , 1993, Symposium 1993 on VLSI Technology.
[12] F. Assaderaghi,et al. Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance , 1994, IEEE Electron Device Letters.
[13] O. Faynot,et al. High performance ultrathin SOI MOSFET's obtained by localized oxidation , 1994, IEEE Electron Device Letters.
[14] Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's , 1994, IEEE Electron Device Letters.
[15] Comparison of Standard and Low-Dose SIMOX Substrates for 0.15μm SOI MOSFET Applications , 1995 .
[16] C. Hu,et al. A comparative study of advanced MOSFET concepts , 1996 .
[17] T. Sugii,et al. Novel shallow junction technology using decaborane (B/sub 10/H/sub 14/) , 1996, International Electron Devices Meeting. Technical Digest.
[18] S. Talwar,et al. Characterization of reverse leakage components for ultrashallow p+/n diodes fabricated using gas immersion laser doping , 1996, IEEE Electron Device Letters.
[19] Ultra-shallow junction formation using very low energy B and BF/sub 2/ sources , 1996, Proceedings of 11th International Conference on Ion Implantation Technology.
[20] H.-S.P. Wong,et al. Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[21] D. Frank,et al. Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[22] Ultra Shallow Junction Formation by B+/BF2+ Implantation at Energy of 0.5 KEV , 1998 .
[23] M. Mendicino,et al. PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[24] T. Sugii,et al. Ultra Shallow Junction Formation by Cluster Ion Implantation , 1998 .
[25] T. Sugii,et al. A study of ultra shallow junction and tilted channel implantation for high performance 0.1 /spl mu/m pMOSFETs , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[26] 33 nm ultra-shallow junction technology by oxygen-free and point-defect reduction process , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
[27] G.A. Brown,et al. CMOS metal replacement gate transistors using tantalum pentoxide gate insulator , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[28] Evaluation of plasma doping for sub-0.18 /spl mu/m devices , 1998, 1998 International Conference on Ion Implantation Technology. Proceedings (Cat. No.98EX144).
[29] G. de Cock,et al. Uniform spike anneals of ultra low energy boron implants using xR LEAP and RTP Centura XE/sub plus/: ramp rate effects up to 150/spl deg/C/sec , 1998, 1998 International Conference on Ion Implantation Technology. Proceedings (Cat. No.98EX144).
[30] Advanced processing technique to minimize enhanced diffusion in sub-keV boron implants , 1999, 1998 International Conference on Ion Implantation Technology. Proceedings (Cat. No.98EX144).
[31] T. Mogami,et al. High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
[32] T. Skotnicki,et al. Heavily doped and extremely shallow junctions on insulator by SONCTION (SilicON Cut-off juncTION) process , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[33] T. Skotnicki. Polysilicon gate with depletion-or-metallic gate with buried channel: what evil worse ? , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[34] R. Koh. Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET , 1999 .
[35] T. Skotnicki,et al. SON (silicon on nothing)-a new device architecture for the ULSI era , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
[36] Reliable and enhanced performances of sub-0.1 /spl mu/m pMOSFETs doped by low biased plasma doping , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).
[37] Hiroshi Hiroshima,et al. Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs , 2000 .