SOI technology for the GHz era

Silicon on Insulator (SOI) CMOS offers 20-35% performance gain over bulk CMOS. High performance microprocessors using SOI CMOS have been shipping since 1998. As we move to 0.13 /spl mu/m generation, it will be used by more companies, and spread to lower-end microprocessors and SRAMs. In this paper, after a short history of SOI in IBM, we will describe causes of performance gain on SOI, and its scalability to 0.1 /spl mu/m generation and beyond. Some of the recent applications of SOI in high-end microprocessors will be described. It is fully expected that as we move to 0.1 /spl mu/m and beyond, SOI is the technology of choice for applications which require high performance, and/or low power.

[1]  R. Dennard,et al.  History dependence of non-fully depleted (NFD) digital SOI circuits , 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

[2]  S. Narasimha,et al.  A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[3]  Tak H. Ning,et al.  A room temperature 0.1 /spl mu/m CMOS on SOI , 1994 .

[4]  L. Wagner,et al.  Transient pass-transistor leakage current in SOI MOSFET's , 1997, IEEE Electron Device Letters.

[5]  Robert Hannon,et al.  0.25 /spl mu/m merged bulk DRAM and SOI logic using patterned SOI , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).