A monolithic 14 bit A/D converter

A 14 bit monolithic successive approximation A/D converter with 7 /spl mu/s conversion time is described. A special system called `dynamic element matching' is used to construct the high-accuracy D/A converter needed in the system. The high linearity of the converter (/spl plusmn//SUP 1///SUB 4/ LSB) results in an 84 dB S/N ratio. The high-speed comparator consists of a wide-band (75 MHz) clamped operational amplifier followed by a strobed flip-flop to freeze the output data. In the digital part, current mode logic (CML) is used for speed and low interference generation with respect to the analog circuitry. Digital input and outputs are TTL compatible. A low-noise, high-stability reference source with a temperature dependence of /spl plusmn/0.5 ppm//spl deg/C over -20 to +85/spl deg/C completes the A/D function. The chip is processed in a standard bipolar process using double layer interconnection. The die size is 3.5/spl times/4.4 mm/SUP 2/.