As applications requiring a lot of memory grows, memory-centric computing systems which has a lot of memory pool are drawing attention. And the high-speed interconnection for accessing memory pools in this system is a very important part. In this paper, the bridge hardware for connecting PCI Express bus which is widely used in general systems, to Gen-Z protocol adapter which is one of the new high-speed networks, is shown, and its maximum performance is measured. This hardware has shown that it can support up to 720MB/s for memory writes and 3.5GB/s for block writes. This bridge hardware is expected to upgrade the performance of existing hardware and can expand the application field of the Gen-Z memory system.
[1]
Myeong-Hoon Oh,et al.
Signal integrity analysis of system interconnection module of high‐density server supporting serial RapidIO
,
2019
.
[2]
Seokbin Hong,et al.
Hardware Implementation and Analysis of Gen-Z Protocol for Memory-Centric Architecture
,
2020,
IEEE Access.
[3]
Rachata Ausavarungnirun,et al.
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks
,
2018,
ASPLOS.
[4]
Myeong-Hoon Oh,et al.
Implementation and Analysis of a memory-semantic interconnect based on Gen-Z Protocol
,
2020,
2020 IEEE International Conference on Consumer Electronics - Asia (ICCE-Asia).