A numerical study of field plate configurations in RF SOI LDMOS transistors

The effect of the source field plate architecture on the static and dynamic electrical performances of SOI LDMOS transistors for RF applications is analysed in this paper. Three architectures are envisaged: source field plate SFP, extended gate field plate and independently biased field plate. Moreover, two different drift diffusion profiles are considered: shallow SDD and deep doped DDD diffusion. The resultant drift region is analytically modelled and the impact of geometrical and technological parameters on the transconductance value is determined by means of numerical simulation techniques. Finally, the dependence of the LDMOS capacitances on the field plate configuration is also studied. Simulation results show the trade-off between reliability and transconductance in each field plate configuration. In spite of the power efficiency improvement, the field plate biasing can significantly degrade the SOI LDMOS performances due to hot-carrier and self-heating effects. On the contrary, the SFP configuration leads to an enhanced reliability at the cost of the on-state resistance increase. The SFP structure with deep doped drift (DDD) diffusion provides the best performances in terms of cut-off frequency and self-heating degradation.

[1]  G. D. Vendelin,et al.  D-MOS transistor for microwave applications , 1972 .

[2]  A.M. Ionescu,et al.  Physical modelling strategy for (quasi-) saturation effects in lateral DMOS transistor based on the concept of intrinsic drain voltage , 2001, 2001 International Semiconductor Conference. CAS 2001 Proceedings (Cat. No.01TH8547).

[3]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[4]  Jaume Roig,et al.  Modeling of non-uniform heat generation in LDMOS transistors , 2005 .

[5]  E.M.S. Narayanan,et al.  Comparative study of drift region designs in RF LDMOSFETs , 2004, IEEE Transactions on Electron Devices.

[6]  Krishna Shenai,et al.  Modeling and characterization of an 80 V silicon LDMOSFET for emerging RFIC applications , 1998 .

[7]  G. Groeseneken,et al.  Hot-carrier degradation phenomena in lateral and vertical DMOS transistors , 2004, IEEE Transactions on Electron Devices.

[8]  T. Manku,et al.  Microwave CMOS-device physics and design , 1999, IEEE J. Solid State Circuits.

[9]  Krishna Shenai,et al.  Performance modeling of RF power MOSFETs , 1999 .

[10]  Jerry G. Fossum,et al.  New physical insights and models for high-voltage LDMOST IC CAD , 1991 .

[11]  F. van Rijs,et al.  Record power added efficiency of bipolar power transistors for low voltage wireless applications , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[12]  G. Cao,et al.  A high performance RF LDMOSFET in thin film SOI technology with step drift profile , 2003 .

[13]  David Flores,et al.  Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile , 2005, Microelectron. Reliab..

[14]  Yong Liu,et al.  RF LDMOS with extreme low parasitic feedback capacitance and high hot-carrier immunity , 1999 .

[15]  B. Hofflinger,et al.  A 100-V lateral DMOS transistor with a 0.3-micrometer channel in a 1-micrometer silicon-film-on-insulator-on-silicon , 1991 .

[16]  Denis Flandre,et al.  Substrate crosstalk reduction using SOI technology , 1997 .