Modeling and Tuning of an Improved Delayed-Signal-Cancellation PLL for Microgrid Application

An improved delayed-signal-cancellation (DSC) phase-locked loop (PLL) is proposed for microgrid applications. The conventional DSC-PLL suffers from phase and frequency measurement errors due to a fixed delay operation within the control loop. The source of this error is mathematically analyzed in this paper. The modified DSC-PLL model overcomes the error by using a positive sequence $\alpha \beta$ detector and a notch filter. The proposed method not only rejects the double frequency oscillation appearing at the output of the PLL under unbalanced loading conditions but also offers good harmonic rejection with nonlinear loads. The proposed model adds minimal complexity to the existing DSC-PLL. To ensure a fast dynamic response as well as a stable operation, a systematic approach is proposed to design the controller gains and filter parameters. The newly designed PLL is simulated and tested for performance verification purposes.

[1]  Josep M. Guerrero,et al.  An Efficient Implementation of Generalized Delayed Signal Cancellation PLL , 2016, IEEE Transactions on Power Electronics.

[2]  Josep M. Guerrero,et al.  dq-Frame Cascaded Delayed Signal Cancellation- Based PLL: Analysis, Design, and Comparison With Moving Average Filter-Based PLL , 2015, IEEE Transactions on Power Electronics.

[3]  Juan C. Vasquez,et al.  Three-Phase PLLs: A Review of Recent Advances , 2017, IEEE Transactions on Power Electronics.

[4]  Zhe Chen,et al.  Multiple-Complex Coefficient-Filter-Based Phase-Locked Loop and Synchronization Technique for Three-Phase Grid-Interfaced Converters in Distributed Utility Networks , 2011, IEEE Transactions on Industrial Electronics.

[5]  Fang Zhuo,et al.  A Three-Phase PLL Algorithm Based on Signal Reforming Under Distorted Grid Conditions , 2015, IEEE Transactions on Power Electronics.

[6]  Byung-Moon Han,et al.  FPGA based DSC-PLL for grid harmonics and voltage unbalance effect elimination , 2015, 2015 IEEE Applied Power Electronics Conference and Exposition (APEC).

[7]  Kaushik Rajashekara,et al.  An improved delayed signal cancellation PLL for fast grid synchronization under distorted and unbalanced grid condition , 2017, 2016 IEEE Industry Applications Society Annual Meeting.

[8]  Hee-Je Kim,et al.  A Novel Grid Synchronization PLL Method Based on Adaptive Low-Pass Notch Filter for Grid-Connected PCS , 2014, IEEE Transactions on Industrial Electronics.

[9]  Josep M. Guerrero,et al.  Second order generalized integrator based reference current generation method for single-phase shunt active power filters under adverse grid conditions , 2013, 4th Annual International Power Electronics, Drive Systems and Technologies Conference.

[10]  D. Boroyevich,et al.  Decoupled Double Synchronous Reference Frame PLL for Power Converters Control , 2007, IEEE Transactions on Power Electronics.

[11]  Chia-Chi Chu,et al.  Three-phase grid synchronization PLL using multiple delayed signal cancellation under adverse grid voltage conditions , 2017, 2017 IEEE Industry Applications Society Annual Meeting.

[12]  Hanju Cha,et al.  A new DSC-PLL using recursive discrete fourier transform for robustness to frequency variation , 2016, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC).

[13]  Se-Kyo Chung,et al.  A phase tracking system for three phase utility interface inverters , 2000 .

[14]  Math Bollen,et al.  Mitigation of unbalanced voltage dips using static series compensator , 2003, IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468).

[15]  G. C. Paap,et al.  Symmetrical components in the time domain and their application to power network calculations , 2000 .

[16]  Yun Wei Li,et al.  Grid synchronization PLL based on cascaded delayed signal cancellation , 2010, 2010 IEEE Energy Conversion Congress and Exposition.

[17]  Y. Li,et al.  Analysis and Digital Implementation of Cascaded Delayed-Signal-Cancellation PLL , 2011, IEEE Transactions on Power Electronics.

[18]  H. Cha,et al.  Analysis on recursive discrete fourier transform FLL based on delayed signal cancellation-PLL method under frequency variations , 2017, 2017 20th International Conference on Electrical Machines and Systems (ICEMS).

[19]  Josep M. Guerrero,et al.  Small-Signal Modeling, Stability Analysis and Design Optimization of Single-Phase Delay-Based PLLs , 2016, IEEE Transactions on Power Electronics.

[20]  Dazhi Wang,et al.  DC-offset elimination method for grid synchronisation , 2017 .

[21]  Hany A. Hamed,et al.  Frequency Adaptive CDSC-PLL Using Axis Drift Control Under Adverse Grid Condition , 2017, IEEE Transactions on Industrial Electronics.

[22]  Josep M. Guerrero,et al.  Hybrid Adaptive/Nonadaptive Delayed Signal Cancellation-Based Phase-Locked Loop , 2017, IEEE Transactions on Industrial Electronics.

[23]  E.J. Bueno,et al.  SPLL design to flux oriented of a VSC interface for wind power applications , 2005, 31st Annual Conference of IEEE Industrial Electronics Society, 2005. IECON 2005..

[24]  M. Karimi-Ghartemani,et al.  Addressing DC Component in PLL and Notch Filter Algorithms , 2012, IEEE Transactions on Power Electronics.

[25]  Jonathan W. Kimball,et al.  An Accurate Small-Signal Model of Inverter- Dominated Islanded Microgrids Using $dq$ Reference Frame , 2014, IEEE Journal of Emerging and Selected Topics in Power Electronics.

[26]  F. Blaabjerg,et al.  Symmetrical components and power analysis for a two-phase microgrid system , 2014, 2014 Power and Energy Conference at Illinois (PECI).

[27]  Frede Blaabjerg,et al.  Multiresonant Frequency-Locked Loop for Grid Synchronization of Power Converters Under Distorted Grid Conditions , 2011, IEEE Transactions on Industrial Electronics.

[28]  J. Svensson,et al.  Tuning software phase-locked loop for series-connected converters , 2005, IEEE Transactions on Power Delivery.

[29]  Scott D. Sudhoff,et al.  A multiple reference frame synchronous estimator/regulator , 2000 .

[30]  Yingpin Wang,et al.  Fast convergence and linear modeling of adaptive cascaded delayed signal cancellation-PLL , 2016, 2016 IEEE International Conference on Renewable Energy Research and Applications (ICRERA).

[31]  Francisco A. S. Neves,et al.  A Method for Extracting the Fundamental-Frequency Positive-Sequence Voltage Vector Based on Simple Mathematical Transformations , 2008, IEEE Transactions on Industrial Electronics.

[32]  Marco Liserre,et al.  New Positive-sequence Voltage Detector for Grid Synchronization of Power Converters under Faulty Grid Conditions , 2006 .

[33]  M. Monfared,et al.  Design-Oriented Study of Advanced Synchronous Reference Frame Phase-Locked Loops , 2013, IEEE Transactions on Power Electronics.

[34]  Claus Leth Bak,et al.  Analysis and design of notch filter-based PLLs for grid-connected applications , 2017 .

[35]  Josep M. Guerrero,et al.  Five Approaches to Deal With Problem of DC Offset in Phase-Locked Loop Algorithms: Design Considerations and Performance Evaluations , 2016, IEEE Transactions on Power Electronics.