Layout optimization of planar CMOS cells regarding width-to-height trade-off

A new area optimizing transistor placement algorithm for CMOS complex gate layout synthesis is presented. The algorithm handles dual planar CMOS circuits and regards cell width reduction by systematical jog insertion. A study comprising 3503 series-parallel and 423 non-series-parallel CMOS circuits shows, that cell area can be reduced by up to 52% through placement optimization, compared to previous approaches.

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