A 10-bit fast lock all-digital data recovery with CR oscillator reference for automotive network

This paper proposes a fast lock data recovery method operating with the inaccurate and higher jitter reference clock such as the CR oscillator. The proposed circuit consists of a blind oversampling deserializer and a data recovery logic circuit. And this circuit decides the consecutive bits' number by the bit-boundary estimation. The estimation calculated only from the past 10 bit-transition timing enables the fast lock and higher jitter tracking performance. Experimental results demonstrated that the FPGA based test circuit has the jitter tolerance corner frequency of 3MHz, that is relatively 10 times higher than the conventional clock and data recovery (CDR) technology under -20 ~ +30% wide offset of reference frequency and 0.2UI peak to peak random jitter.