RAM-Based Neural Network Parallel Implementation on a Reconfigurable Platform and Its Application for Handwritten Digits Recognition

Artificial neural networks (ANNs) are widely used in different areas of nowadays applications. Many challenges are imposed on the practical implementation of ANNs. Some of them are: the number of samples required to train the network; the number of adders, multipliers, nonlinear transfer functions, storage elements; and the speed of calculations in either training phase or recall phase. In this paper, the RAM-based neural network is investigated. No weights, adders, multipliers, transfer functions are required to implement it neither in hardware nor in software, but at a cost of large RAM utilization. In addition, a small number of samples are required for training. However, in hardware implementation, a large size of memory is required to train it. The network is implemented on the FPGA platform. The Stratix IV GX FPGA development board, which is provided on large on board RAM, is used. A considerable speedup of 237 is achieved in either training or recalling phases. A comparable error rate of 7.6 is achieved when MNIST (Mixed National Institute of Standards and Technology) database are used to train the network on handwritten digit recognition.

[1]  K. P. Lakshmi,et al.  A Survey on FPGA based MLP Realization for On-chip Learning , 2013 .

[2]  Alberto Ferreira de Souza,et al.  Multi-label Text Categorization Using VG-RAM Weightless Neural Networks , 2008, 2008 10th Brazilian Symposium on Neural Networks.

[3]  Marc'Aurelio Ranzato,et al.  Efficient Learning of Sparse Representations with an Energy-Based Model , 2006, NIPS.

[4]  Jim Austin.  A review of RAM based neural networks , 1994, Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems.

[5]  Yoshua Bengio,et al.  Gradient-based learning applied to document recognition , 1998, Proc. IEEE.

[6]  Yiorgos Makris,et al.  A dual-mode weight storage analog neural network platform for on-chip applications , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[7]  Nadia Nedjah,et al.  Reconfigurable hardware for neural networks: binary versus stochastic , 2007, Neural Computing and Applications.