Design for Testability Techniques for CMOS

This paper deals with the design of easily testable CMOS combinational circuits. Two CMOS structured design techniques are presented. The novelty of this approach is the complete fault detection of single- and multiple-line stuck-at, transistor stuck-open, and stuck-on faults for combinational circuits. The test algorithm requires only minimal modifica- tions to detect a large number of bridging faults. These tech- niques are both based on the addition of two transistors, a P-FET and an N-FET, which are placed in series between the P and N sections. In the first case (Dyanmic Fully CMOS- DFCMOS), the transistors are controlled by a single input; in the other case (Testable Fully CMOS-TFCMOS), there is one input for each additional transistor. The test procedure is pre- sented and it is shown that multiple fault detection can be easily achieved.