In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
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[1] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[2] Johnny Öberg,et al. Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[3] Hannu Tenhunen,et al. Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).
[4] Michael Nicolaidis,et al. Theory of Transparent BIST for RAMs , 1996, IEEE Trans. Computers.
[5] Kaushik Roy,et al. Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era , 2010, Proceedings of the IEEE.
[6] Arnaud Virazel,et al. Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test , 2005, J. Electron. Test..
[7] A.J. van de Goor,et al. Functional tests for arbitration SRAM-type FIFOs , 1992, Proceedings First Asian Test Symposium (ATS `92).
[8] Dong Xiang,et al. A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing , 2013, 2013 22nd Asian Test Symposium.
[9] Andrea Bondavalli,et al. Threshold-Based Mechanisms to Discriminate Transient from Intermittent Faults , 2000, IEEE Trans. Computers.
[10] Luca Benini,et al. A distributed and topology-agnostic approach for on-line NoC testing , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.
[11] Ye Zhang,et al. Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] Franco Fummi,et al. A parametric design of a built-in self-test FIFO embedded memory , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[13] Santanu Chattopadhyay,et al. Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router , 2012, Microprocess. Microsystems.
[14] Axel Jantsch,et al. Methods for fault tolerance in networks-on-chip , 2013, CSUR.
[15] Partha Pratim Pande,et al. Methodologies and algorithms for testing switch-based NoC interconnects , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).