Implementation of Application Specific Network-On-Chip Architectures on Reconfigurable Device Using Topology Generation Algorithm with Genetic Algorithm Based Optimization Technique

In Networks-On-Chip (NOC) architecture, routers are the main sources of power consumption. Hence to reduce the power consumption, the application should be mapped on a custom topology rather than on regular topologies, as custom topology uses fewer routers than regular topologies. This reduces the power consumption. In this paper, we propose a novel topology generation algorithm using genetic algorithm optimization technique to generate a custom topology for Application Specific Networks-On-Chip (ASNOC) architectures. We applied the novel algorithm to benchmark video applications MPEG 4 decoder and PIP. The implementation of the proposed algorithm on Altera cyclone II FPGA device EP2C35F672C6 shows good results in terms of area, power consumption, hop count and number of global links compared to standard topologies like Mesh, Ring, Star and Binary Tree.

[1]  Krishnan Srinivasan,et al.  A technique for low energy mapping and routing in network-on-chip architectures , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[2]  Suleyman Tosun,et al.  TopGen: A new algorithm for automatic topology generation for Network on Chip architectures to reduce power consumption , 2009, 2009 International Conference on Application of Information and Communication Technologies.

[3]  Krishnan Srinivasan,et al.  Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  L. Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[5]  Xiaola Lin,et al.  Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique , 2011, The Journal of Supercomputing.

[6]  Partha Pratim Pande,et al.  Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.

[7]  Radu Marculescu,et al.  Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures , 2003, DATE.

[8]  Kees G. W. Goossens,et al.  A unified approach to constrained mapping and routing on network-on-chip architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[9]  Gul N. Khan,et al.  Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Krishnan Srinivasan,et al.  An automated technique for topology and route generation of application specific on-chip interconnection networks , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[11]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[12]  Krishnan Srinivasan,et al.  Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[13]  Tapani Ahonen,et al.  Topology optimization for application-specific networks-on-chip , 2004, SLIP '04.

[14]  Deepak Majeti,et al.  Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia Applications , 2009, 2009 Second International Conference on Emerging Trends in Engineering & Technology.

[15]  Glenn Leary,et al.  Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  K.-C. Chang,et al.  Low-power algorithm for automatic topology generation for application-specific networks on chips , 2008, IET Comput. Digit. Tech..

[17]  Radu Marculescu,et al.  Challenges and Promising Results in NoC Prototyping Using FPGAs , 2007, IEEE Micro.

[18]  Luca Benini,et al.  Network-on-Chip design and synthesis outlook , 2008, Integr..

[19]  Haytham Elmiligi,et al.  Power optimization for application-specific networks-on-chips: A topology-based approach , 2009, Microprocess. Microsystems.

[20]  Timothy Mark Pinkston,et al.  A methodology for designing efficient on-chip interconnects on well-behaved communication patterns , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[21]  Miltos D. Grammatikakis,et al.  NoC Topologies Exploration based on Mapping and Simulation Models , 2007 .

[22]  Balasubramanian Sethuraman.  Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices , 2007 .