The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems
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Luciano Lavagno | Jordi Cortadella | Michael Kishinevsky | Alex Kondratyev | Alexander Taubin | L. Lavagno | J. Cortadella | A. Taubin | A. Kondratyev | M. Kishinevsky
[1] Teresa H. Y. Meng,et al. Asynchronous design for programmable digital signal processors , 1991, IEEE Trans. Signal Process..
[2] G. Goossens,et al. A generalized state assignment theory for transformations on signal transition graphs , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[3] Randal E. Bryant,et al. Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.
[4] Tam-Anh Chu,et al. Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .
[5] C. Petri. Kommunikation mit Automaten , 1962 .
[6] Carla Simone,et al. A survey of equivalence notions for net based systems , 1992, Advances in Petri Nets: The DEMON Project.
[7] Michel Hack,et al. ANALYSIS OF PRODUCTION SCHEMATA BY PETRI NETS , 1972 .
[8] Victor Varshavsky,et al. Asynchronous Control Device Design by Net Model Behavior Simulation , 1996, Application and Theory of Petri Nets.
[9] Michael Kishinevsky,et al. A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings , 1996, Application and Theory of Petri Nets.
[10] Luciano Lavagno,et al. Technology mapping for speed-independent circuits: Decomposition and resynthesis , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[11] Frank Thomson Leighton,et al. Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits , 1988 .
[12] Jordi Cortadella,et al. Petri Net Analysis Using Boolean Manipulation , 1994, Application and Theory of Petri Nets.
[13] Luciano Lavagno,et al. Algorithms for Synthesis and Testing of Asynchronous Circuits , 1993 .
[14] Volker Diekert,et al. Combinatorics on Traces , 1990, Lecture Notes in Computer Science.
[15] Michael Yoeli,et al. Specification and verification of asynchronous circuits using marked graphs , 1987 .
[16] Alexandre Yakovlev,et al. Modelling, analysis and synthesis of asynchronous control circuits using Petri nets , 1996, Integr..
[17] Teresa H. Y. Meng,et al. Synthesis of Timed Asynchronous CircuitsChris , 1993 .
[18] Jordi Cortadella,et al. Hierarchical gate-level verification of speed-independent circuits , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.
[19] Hugo De Man,et al. Optimized synthesis of asynchronous control circuits from graph-theoretic specifications , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[20] Alex Kondratyev,et al. Verification of the speed-independent circuits by STG unfoldings , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.
[21] Giovanni De Micheli,et al. Decomposition methods for library binding of speed-independent asynchronous designs , 1994, ICCAD.
[22] Grzegorz Rozenberg,et al. Elementary Transition Systems , 1990, Theor. Comput. Sci..
[23] Giovanni De Micheli,et al. Algorithms for technology mapping based on binary decision diagrams and on Boolean operations , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Kenneth L. McMillan,et al. A technique of state space search based on unfolding , 1995, Formal Methods Syst. Des..
[25] Hugo De Man,et al. A generalized state assignment theory for transformations on signal transition graphs , 1994, J. VLSI Signal Process..
[26] Wolfgang Reisig. Petri Nets: An Introduction , 1985, EATCS Monographs on Theoretical Computer Science.
[27] C. A. R. Hoare,et al. Communicating sequential processes , 1978, CACM.
[28] Chen-Shang Lin,et al. A realization algorithm of asynchronous circuits from STG , 1992, [1992] Proceedings The European Conference on Design Automation.
[29] Patrice Godefroid. Using Partial Orders to Improve Automatic Verification Methods , 1990, CAV.
[30] Manfred Droste. Event Structures and Domains , 1989, Theor. Comput. Sci..
[31] Peter A. Beerel. CAD tools for the synthesis, verification, and testability of robust asynchronous circuits , 1995 .
[32] Steve Furber. Computing without Clocks: Micropipelining the ARM Processor , 1995 .
[33] Alexandre Yakovlev. On limitations and extensions of STG model for designing asynchronous control circuits , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[34] Steven M. Burns,et al. General conditions for the decomposition of state holding elements , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[35] Jörg Desel,et al. Free choice Petri nets , 1995 .
[36] Jordi Cortadella,et al. Structural methods for the synthesis of speed-independent circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[37] Michael Kishinevsky,et al. Concurrent hardware : the theory and practice of self-timed design , 1993 .
[38] Ivan E. Sutherland,et al. Micropipelines , 1989, Commun. ACM.
[39] Jordi Cortadella,et al. Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs , 1993, ICCAD.
[40] Luciano Lavagno,et al. Synthesizing Petri nets from state-based models , 1995, ICCAD.
[41] Tadao Murata,et al. Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.
[42] Luciano Lavagno,et al. Designing asynchronous circuits from behavioural specifications with internal conflicts , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.
[43] Walter Vogler,et al. An Improvement of McMillan's Unfolding Algorithm , 1996, Formal Methods Syst. Des..
[44] Victor I. Varshavsky,et al. Self-Timed Control of Concurrent Processes , 1989 .
[45] Alexandre Yakovlev,et al. Checking signal transition graph implementability by symbolic BDD traversal , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[46] P. S. Thiagarajan,et al. On the Interconnection of Asynchronous Control Structures , 1975, JACM.
[47] Javier Esparza,et al. Model Checking Using Net Unfoldings , 1993, Sci. Comput. Program..
[48] Luciano Lavagno,et al. Complete state encoding based on the theory of regions , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.