Early power estimation for VLSI circuits

Early power estimation, a requirement for design exploration early in the design phase, must often be done based on a design specification that is available only at a high level of abstraction. One way of doing this is to use high-level estimation of circuit total capacitance and average activity. This paper addresses these problems and proposes a high-level area estimation technique based on the complexity of a Boolean network representation of the design. In addition to the high-level area estimation, the paper also proposes a high-level activity estimation methodology that is capable of handling correlated input streams. High-level power estimates based on the total capacitance and average activity estimates are also given.

[1]  Enrico Macii,et al.  Parameterized RTL power models for soft macros , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Mahadevamurty Nemani High-Level Power Estimation , 1998 .

[3]  Farid N. Najm,et al.  Statistical Estimation of the Switching Activity in Digital Circuitsy , 1994, 31st Design Automation Conference.

[4]  Athanasios Papoulis,et al.  Probability, Random Variables and Stochastic Processes , 1965 .

[5]  David E. Muller,et al.  Complexity in Electronic Switching Circuits , 1956, IRE Trans. Electron. Comput..

[6]  Farid N. Najm,et al.  Towards a high-level power estimation capability [digital ICs] , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Luca Benini,et al.  Node sampling: a robust RTL power modeling approach , 1998, ICCAD.

[10]  Farid N. Najm,et al.  Power modeling for high-level power estimation , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[11]  I. Miller Probability, Random Variables, and Stochastic Processes , 1966 .

[12]  Claude E. Shannon,et al.  The synthesis of two-terminal switching circuits , 1949, Bell Syst. Tech. J..

[13]  Farid N. Najm,et al.  High-level area and power estimation for VLSI circuits , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[14]  Nicholas Pippenger Information theory and the complexity of boolean functions , 2005, Mathematical systems theory.

[15]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[16]  P. M. Chau,et al.  A model for estimating power dissipation in a class of DSP VLSI chips , 1991 .

[17]  Farid N. Najm,et al.  On the Tunability of a High-Level Area Model , 2002 .

[18]  Farid N. Najm,et al.  High-level area estimation , 2002, ISLPED '02.

[19]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[21]  Priyadarsan Patra A Perspective on Power Issues for Ultra DSM Circuits , 2000 .

[22]  Farid N. Najm,et al.  Towards a high-level power estimation capability , 1995, ISLPED '95.

[23]  Vishwani D. Agrawal,et al.  An entropy measure for the complexity of multi-output Boolean functions , 1991, DAC '90.

[24]  Farid N. Najm,et al.  Transition density: a new measure of activity in digital circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[26]  Farid N. Najm,et al.  Analytical models for RTL power estimation of combinational andsequential circuits , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..