A CMOS PWM Transceiver Using Self-Referenced Edge Detection

A CMOS pulsewidth modulation (PWM) transceiver circuit that exploits the self-referenced edge detection technique is presented. By comparing the rising edge that is self-delayed by about 0.5 T and the modulated falling edge in one carrier clock cycle, area-efficient and high-robustness (against timing fluctuations) edge detection enabling PWM communication is achieved without requiring elaborate phase-locked loops. Since the proposed self-referenced edge detection circuit has the capability of timing error measurement while changing the length of self-delay element, adaptive data-rate optimization and delay-line calibration are realized. The measured results with a 65-nm CMOS prototype demonstrate a 2-bit PWM communication, high data rate (3.2 Gb/s), and high reliability (BER> 10-12) with small area occupation (540 μm2). For reliability improvement, error check and correction associated with intercycle edge detection is introduced and its effectiveness is verified by 1-bit PWM measurement.

[1]  Chih-Cheng Hsieh,et al.  A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise , 2012, 2012 IEEE International Solid-State Circuits Conference.

[2]  Takahiro J. Yamaguchi,et al.  CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation , 2012, IEEE Journal of Solid-State Circuits.

[3]  John A. McNeill.  Jitter in ring oscillators , 1997 .

[4]  Kiichi Niitsu,et al.  Charge-conserved analog-to-time converter for a large-scale CMOS biosensor array , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[5]  Greg Unruh,et al.  An 8.5 mW, 0.07 mm2 ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter , 2013, 2013 Symposium on VLSI Circuits.

[6]  Shen-Iuan Liu,et al.  A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme , 2001 .

[7]  Ramesh Harjani,et al.  FEXT Crosstalk Cancellation for High-Speed Serial Link Design , 2006, IEEE Custom Integrated Circuits Conference 2006.

[8]  Takahiro J. Yamaguchi,et al.  A clock jitter reduction circuit using gated phase blending between self-delayed clock edges , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[9]  Deog-Kyoon Jeong,et al.  A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme , 2007, IEEE Journal of Solid-State Circuits.

[10]  Ching-Yuan Yang,et al.  A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers , 2008, IEEE Transactions on Instrumentation and Measurement.

[11]  Davide De Caro,et al.  A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[12]  K. Ichiyama,et al.  A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[13]  Yuka Kobayashi,et al.  A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.