Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware

This paper discusses some aspects regarding the use of universal linear threshold elements implemented in a standard double-poly CMOS technology, which might be used for neural networks as well as plain, or mixed-signal, analog and digital circuits. The 2-transistor elements can have their threshold adjusted in real time, and thus the basic Boolean function, by changing the voltage on one or more of the inputs. The proposed elements allow for significant reduction in transistor count and number of interconnections. This in combination with a power supply voltage in the range of less than 100 mV up to typically 1.0 V allow for Power-Delay-product improvements typically in the range of hundreds to thousands of times compared to standard implementations in a 0.6 micron CMOS technology. This makes the circuits more similar to biological neurons than most existing CMOS implementations. Circuit examples are explored by theory, SPICE simulations and chip measurements. A way of exploiting inherit fault tolerance is briefly mentioned. Potential improvements on operational speed and chip area of linear threshold elements used for perceptual tasks are shown.

[1]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[2]  Snorre Aunet,et al.  Four-MOSFET Floating-Gate UV-Programmable Elements for Multifunction Binary Logic , 2001 .

[3]  Tor Sverre Lande,et al.  Overview of floating-gate devices, circuits, and systems , 2001 .

[4]  Dan W. Hammerstrom,et al.  Computational neurobiology meets semiconductor engineering , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

[5]  Jehoshua Bruck,et al.  Depth efficient neural networks for division and related problems , 1993, IEEE Trans. Inf. Theory.

[6]  Snorre Aunet.  Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS , 2002 .

[7]  T.S. Lande,et al.  Low-voltage floating-gate current mirrors , 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

[8]  Kenneth R. Laker,et al.  Design of analog integrated circuits and systems , 1994 .

[9]  Vasken Zaven Bohossian,et al.  Neural logic: theory and implementation , 1998 .

[10]  Jehoshua Bruck,et al.  Neural computation of arithmetic functions , 1990 .

[11]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[12]  Tadahiro Ohmi,et al.  An intelligent MOS transistor featuring gate-level weighted sum and threshold operations , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[13]  Tor Sverre Lande,et al.  FLOGIC-Floating-gate logic for low-power operation , 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

[14]  Yngvar Berg,et al.  Ultra low-voltage/low-power digital floating-gate circuits , 1999 .

[15]  P.P. Gelsinger,et al.  Microprocessors for the new millennium: Challenges, opportunities, and new frontiers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).