An overview of manufacturing yield and reliability modeling for semiconductor products

This paper presents an overview of yield, reliability, burn-in, cost factors, and fault coverage as practiced in the semiconductor manufacturing industry. Reliability and yield modeling can be used as a foundation for developing effective stress burn-in, which in turn can warranty high-quality semiconductor products. Yield models are described and their advantages and disadvantages are discussed. Both yield reliability relationships and relation models between yield and reliability are thoroughly analyzed in regard to their importance to semiconductor products.

[1]  Way Kuo,et al.  Optimal burn‐in decision making , 1998 .

[2]  Way Kuo,et al.  A relation model of yield and reliability for the gate oxide failures , 1998, Annual Reliability and Maintainability Symposium. 1998 Proceedings. International Symposium on Product Quality and Integrity.

[3]  A. Helland,et al.  Establishing ASIC fault-coverage guidelines for high-reliability systems , 1998, Annual Reliability and Maintainability Symposium. 1998 Proceedings. International Symposium on Product Quality and Integrity.

[4]  Way Kuo,et al.  Reliability, Yield, And Stress Burn-In , 1998 .

[5]  Way Kuo,et al.  A nonparametric Bayes approach to decide system burn‐in time , 1997 .

[6]  T. Turner Wafer level reliability: process control for reliability , 1996, Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.

[7]  E.R. Ooms,et al.  Relation between yield and reliability of integrated circuits and application to failure rate assessment and reduction in the one digit FIT and PPM reliability era , 1996, Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.

[8]  C. N. Berglund,et al.  A unified yield model incorporating both defect and parametric effects , 1996 .

[9]  Way Kuo,et al.  A nonparametric approach to estimate system burn-in time , 1996 .

[10]  Sut-Mui Tang,et al.  New burn-in methodology based on IC attributes, family IC burn-in data, and failure mechanism analysis , 1996, Proceedings of 1996 Annual Reliability and Maintainability Symposium.

[11]  F. Kuper,et al.  Relation between yield and reliability of integrated circuits: experimental results and application to continuous early failure rate reduction programs , 1996, Proceedings of International Reliability Physics Symposium.

[12]  L.N. Lie,et al.  Wafer level reliability procedures to monitor gate oxide quality using V ramp and J ramp test methodology , 1995, IEEE 1995 International Integrated Reliability Workshop. Final Report.

[13]  A. Mathewson,et al.  Assessing MOS gate oxide reliability on wafer level with ramped/constant voltage and current stress , 1995, IEEE 1995 International Integrated Reliability Workshop. Final Report.

[14]  A. Lill,et al.  Implementation of a WLR-program into a production line , 1995, IEEE 1995 International Integrated Reliability Workshop. Final Report.

[15]  P. Chaparala,et al.  A new physics-based model for time-dependent-dielectric-breakdown , 1995, IEEE 1995 International Integrated Reliability Workshop. Final Report.

[16]  B. El-Kareh,et al.  Yield management in microelectronic manufacturing , 1995, 1995 Proceedings. 45th Electronic Components and Technology Conference.

[17]  C. H. Stapper,et al.  Integrated circuit yield management and yield analysis: development and implementation" ieee trans , 1995 .

[18]  Costas J. Spanos,et al.  Semiconductor yield improvement: results and best practices , 1995 .

[19]  Way Kuo,et al.  Modeling and maximizing burn-in effectiveness , 1995 .

[20]  Way Kuo,et al.  Opinions on consecutive-k-out-of-n:F systems , 1994 .

[21]  S. Garrard,et al.  Production implementation of a practical WLR program , 1994, Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS).

[22]  M. Jevtic,et al.  Integrating Reliability into Microelectronics Manufacturing , 1994 .

[23]  D. Gralian,et al.  Next generation burn-in development , 1994 .

[24]  B. Vasquez,et al.  The Promise of Known-good-die Technologies , 1994, Proceedings of the International Conference on Multichip Modules.

[25]  A. D. Singh On Wafer Burn-in Strategies for MCM Die , 1994, Proceedings of the International Conference on Multichip Modules.

[26]  D. Tuckerman,et al.  A Cost-Effective Wafer-Level Burn-In Technology , 1994, Proceedings of the International Conference on Multichip Modules.

[27]  Kunihiko Ikuzaki,et al.  VLSI reliability challenges: from device physics to wafer scale systems , 1993, Proc. IEEE.

[28]  J. Soden,et al.  IC failure analysis: techniques and tools for quality reliability improvement , 1993, Proc. IEEE.

[29]  Francesco Corsi,et al.  Defect level as a function of fault coverage and yield , 1993, Proceedings ETC 93 Third European Test Conference.

[30]  E.M.J.G. Bruls Reliability aspects of defect analysis , 1993, Proceedings ETC 93 Third European Test Conference.

[31]  J. G. Prendergast Reliability, yield and quality correlation for a particular failure mechanism , 1993, 31st Annual Proceedings Reliability Physics 1993.

[32]  T. A. Dellin,et al.  Wafer level reliability , 1993, Other Conferences.

[33]  Chenming Hu,et al.  Future CMOS scaling and reliability , 1993, Proc. IEEE.

[34]  Robert C. Aitken,et al.  Test sets and reject rates: all fault coverages are not created equal , 1993, IEEE Design & Test of Computers.

[35]  Kwei Tang,et al.  Burn‐in Time and Estimation of Change‐Point with Weibull‐Exponential Mixture Distribution* , 1992 .

[36]  Ninoslav Stojadinovic,et al.  New defect size distribution function for estimation of chip critical area in integrated circuit yield models (CMOS) , 1992 .

[37]  H. H. Huston,et al.  Reliability defect detection and screening during processing-theory and implementation , 1992, 30th Annual Proceedings Reliability Physics 1992.

[38]  D. Dance,et al.  Using yield models to accelerate learning curve progress (semiconductor industry) , 1992 .

[39]  Albert V. Ferris-Prabhu,et al.  Introduction To Semiconductor Device Yield Modeling , 1992 .

[40]  M. Haim,et al.  Bayes reliability modeling of a multistate consecutive K-out-of-n: F system , 1991, Annual Reliability and Maintainability Symposium. 1991 Proceedings.

[41]  J. Meindl,et al.  A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy , 1990 .

[42]  L. Leemis,et al.  Burn-In Models and Methods: A Review , 1990 .

[43]  D. L. Crook,et al.  Evolution of VLSI reliability engineering , 1990, 28th Annual Proceedings on Reliability Physics Symposium.

[44]  J. A. Nachlas,et al.  Microelectronic reliability predictions derived from component defect densities , 1990, Annual Proceedings on Reliability and Maintainability Symposium.

[45]  W. Kuo,et al.  Burn-in optimization under reliability and capacity restrictions , 1989 .

[46]  Lawrence M. Leemis,et al.  Component vs. system burn-in techniques for electronic equipment , 1989 .

[47]  Charles H. Stapper,et al.  Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review , 1989, IBM J. Res. Dev..

[48]  Vishwani D. Agrawal,et al.  On the Probability of Fault Occurrence , 1989 .

[49]  C. H. Stapper,et al.  Fact and fiction in yield modeling , 1989 .

[50]  A. V. Ferris-Prabhu,et al.  Defects, Faults and Semiconductor Device Yield , 1989 .

[51]  C. Kooperberg,et al.  Circuit layout and yield , 1988 .

[52]  E. Hnatek Integrated Circuit Quality and Reliability , 2018 .

[53]  D. F. Frost,et al.  A Method for Predicting VLSI-Device Reliability Using Series Models for Failure Mechanisms , 1987, IEEE Transactions on Reliability.

[54]  C. H. Stapper,et al.  On yield, fault distributions, and clustering of particles , 1986 .

[55]  A. V. Ferris-Prabhu,et al.  Defect size variations and their effect on the critical area of VLSI devices , 1985 .

[56]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[57]  Nozer D. Singpurwalla,et al.  A bayesian approach to inference for monotone failure rates , 1985 .

[58]  C. Stapper The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions , 1985 .

[59]  Charles H. Stapper,et al.  Modeling of Defects in Integrated Circuit Photolithographic Patterns , 1984, IBM J. Res. Dev..

[60]  W. Kuo Reliability Enhancement Through Optimal Burn-In , 1984, IEEE Transactions on Reliability.

[61]  Charles H. Stapper,et al.  Modeling of Integrated Circuit Defect Sensitivities , 1983, IBM J. Res. Dev..

[62]  W. Kuo,et al.  Facing the headaches of early failures: A state-of-the-art review of burn-in decisions , 1983 .

[63]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[64]  D. N. P. Murthy,et al.  Optimal Burn-in Time to Minimize Cost for Products Sold Under Warranty , 1982 .

[65]  Brown,et al.  Defect Level as a Function of Fault Coverage , 1981, IEEE Transactions on Computers.

[66]  Walter H. Schroen Process Testing for Reliability Control , 1978, 16th International Reliability Physics Symposium.

[67]  C. Stapper Defect density distribution for LSI yield calculations , 1973 .

[68]  Satoshi Shimada,et al.  Analysis on yield of integrated circuits and a new expression for the yield , 1972 .

[69]  J. E. Price,et al.  A new look at yield of integrated circuits , 1970 .

[70]  B. T. Murphy,et al.  Cost-size optima of monolithic integrated circuits , 1964 .

[71]  J. Wallmark Design considerations for integrated electronic devices , 1960, IRE Transactions on Electron Devices.