RISC design for computer image generation

Abstract The paper describes the design and analysis of an instruction set which is applicable to a RISC processor operating as a geometry engine for computer image generation. A prototype LSI implementation of a fixedpoint pipelined RISC is described. It provides a novel technique with DMA channels direct to the register file, a high-performance multiplier and a high-performance divider. The extension of this approach to a VLSI ASIC version using macrocells from a standard cell library is outlined together with a discussion of the testability issues. Results from an LSI implementation and an ASIC simulation are presented.

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