Temperature-aware MPSoC scheduling for reducing hot spots and gradients

Thermal hot spots and temperature gradients on the die need to be minimized to manufacture reliable systems while meeting energy and performance constraints. In this work, we solve the task scheduling problem for multiprocessor system-on-chips (MPSoCs) using Integer Linear Programming (ILP). The goal of our optimization is minimizing the hot spots and balancing the temperature distribution on the die for a known set of tasks. Under the given assumptions about task characteristics, the solution is optimal. We compare our technique against optimal scheduling methods for energy minimization, energy balancing, and hot spot minimization, and show that our technique achieves significantly better thermal profiles. We also extend our technique to handle workload variations at runtime.

[1]  Vijay V. Vazirani,et al.  Approximation Algorithms , 2001, Springer Berlin Heidelberg.

[2]  Clemens J. M. Lasance Thermally driven reliability issues in microelectronic systems: status-quo and challenges , 2003, Microelectron. Reliab..

[3]  Kaustav Banerjee,et al.  Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Radu Marculescu,et al.  Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[5]  Jinuk Luke Shin,et al.  A Power-Efficient High-Throughput 32-Thread , 2007 .

[6]  Brendan Gregg,et al.  Solaris Performance and Tools: DTrace and MDB Techniques for Solaris 10 and OpenSolaris , 2006 .

[7]  Sani R. Nassif,et al.  Full chip leakage estimation considering power supply and temperature variations , 2003, ISLPED '03.

[8]  Pradip Bose,et al.  Investigating the Effects of Task Scheduling on Thermal Behavior , 2006 .

[9]  Giovanni De Micheli,et al.  Optimization of Reliability and Power Consumption in Systems on a Chip , 2005, PATMOS.

[10]  H. Kufluoglu,et al.  A Computational Model of NBTI and Hot Carrier Injection Time-Exponents for MOSFET Reliability , 2004 .

[11]  Alan J. Weger,et al.  Thermal-aware task scheduling at the system software level , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[12]  Tajana Simunic,et al.  Temperature Aware Task Scheduling in MPSoCs , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[13]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[14]  Francesco Poletti,et al.  Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[15]  R. Viswanath Thermal Performance Challenges from Silicon to Systems , 2000 .

[16]  Luca Benini,et al.  A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[17]  T. N. Vijaykumar,et al.  Heat-and-run: leveraging SMT and CMP to manage power density through the operating system , 2004, ASPLOS XI.

[18]  Fadi J. Kurdahi,et al.  Power-aware scheduling under timing constraints for mission-critical embedded systems , 2001, DAC '01.

[19]  Xiaobo Sharon Hu,et al.  Task scheduling and voltage selection for energy minimization , 2002, DAC '02.

[20]  Pradip Bose,et al.  The case for lifetime reliability-aware microprocessors , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[21]  Mahmut T. Kandemir,et al.  Thermal-aware task allocation and scheduling for embedded systems , 2005, Design, Automation and Test in Europe.

[22]  Massoud Pedram,et al.  Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system , 2006, Asia and South Pacific Conference on Design Automation, 2006..