Stanford University, GTE Laboratories, and the University of Massachusetts at Amherst are members of an ARPA consortium that is experimentally investigating a method for optical contention resolution utilizing optical switches and delay lines. Our CORD* testbed is a two-node, WDM, all-optical, packet switched network with a passive star topology. Each node transmits: (a) 2.488 Gbps payload data at baseband; (b) 16 bit headers at 80 Mbps on a subcarrier frequency, multiplexed on a unique wavelength; and (c) a 2.488 GHz clock pilot tone. Payload data is transmitted in fixed length, ATM-compatible packets (53 bytes) and the headers contain the destination node address. Both the payload data and header are transmitted in a 250 ns slot. Slots are synchronized among all nodes; this is obtained using a conventional PLL to lock onto a reference signal (called PING) generated by a master node. This method is scalable to an arbitrary number of nodes. Our signaling technique is a special case of multiple subcarrier signaling (MSS), which has been proposed as a means to control a WDM network [ I ] , [2]. In our implementation, each node contains one header detector and one payload data receiver. Nodes transmit their headers at a subcarrier frequency unique to the transmitting node, allowing a single photodetector at the header detector to simultaneously receive headers from all nodes. When a header with the receiving node's destination address arrives, the corresponding wavelength is selected for the payload data receiver. Optical switches and delay lines allow data packet contentions to be resolved in the optical domain at the receiver [3]. The short packet slot size (250 ns) and high data rate (2.488 Gbps) require ultra-fast clock recovery at the payload data receiver. We have solved this problem by explicitly transmitting the payload data clock tone (2.488 GHz). The clock tone, baseband data, and header subcarrier are all combined in the microwave domain before being transmitted over a single optical carrier so that only one laser is required per node. Similarly to the payload data receiver, the header detector must recover the header clock within a few bits. Conventional PLL techniques are not nearly fast enough, requiring 10,000 to 100,000 bits I:O complete clock acquisition. Serial over-sampling techniques are also impractical because the recoveiy logic circuits would have to run at extremely high speeds, at least 320 MHz for the 80 Mbps header channel bit rate. We have developed a novel technique, Delay-line Phase Alignment (DPA), to reliably recover the header channel bit stream with digital circuitry niiming at the bit rate, 80 MHz. With DPA, a multi-tap delay line and selector are used to align the received bit stream with the local clock as shown in Figure 1. A preamble is transmitted at the beginning of each header. The DPA module monitors the bit transitions during the preamble and determines the optimum sampling tap to be used for the header bits. Substantial signal processing, including bounce suppression and transition position averaging. is performed by the