Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding

By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density advantage. However, continuous technology scaling makes MLC NAND flash memories increasingly subject to worse raw storage reliability. This paper presents a memory fault tolerance design solution geared to MLC NAND flash memories. The basic idea is to concatenate trellis coded modulation (TCM) with an outer BCH code, which can greatly improve the error correction performance compared with the current design practice that uses BCH codes only. The key is that TCM can well leverage the multi-level storage characteristic to reduce the memory bit error rate and hence relieve the burden of outer BCH code, at no cost of extra redundant memory cells. The superior performance of such concatenated BCH-TCM coding systems for MLC NAND flash memories has been well demonstrated through computer simulations. A modified TCM demodulation approach is further proposed to improve the tolerance to static memory cell defects. We also address the associated practical implementation issues in case of using either single-page or multi-page programming strategy, and demonstrate the silicon implementation efficiency through application-specific integrated circuit design at 65 nm node.

[1]  Roberto Bez,et al.  Introduction to flash memory , 2003, Proc. IEEE.

[2]  T. Takeshima,et al.  A 98 mm/sup 2/ die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell , 1996 .

[3]  G. Ungerboeck,et al.  Trellis-coded modulation with redundant signal sets Part I: Introduction , 1987, IEEE Communications Magazine.

[4]  H.-L. Lou,et al.  Implementing the Viterbi algorithm , 1995, IEEE Signal Process. Mag..

[5]  Yan Li,et al.  A 56-nm CMOS 99-${\hbox {mm}}^{2} $ 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput , 2007, IEEE Journal of Solid-State Circuits.

[6]  UngerboeckG..  Trellis-coded modulation with redundant signal sets Part II , 1987 .

[7]  A. Inoue,et al.  A 70 nm 16 Gb 16-Level-Cell NAND flash Memory , 2008, IEEE Journal of Solid-State Circuits.

[8]  Tong Zhang,et al.  Multilevel flash memory on-chip error correction based on trellis coded modulation , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[9]  G. David Forney,et al.  Coset codes-I: Introduction and geometrical classification , 1988, IEEE Trans. Inf. Theory.

[10]  H. Meyr,et al.  High-speed parallel Viterbi decoding: algorithm and VLSI-architecture , 1991, IEEE Communications Magazine.

[11]  Gerhard Fettweis,et al.  A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Ken Takeuchi,et al.  A multipage cell architecture for high-speed programming multilevel NAND flash memories , 1998, IEEE J. Solid State Circuits.

[13]  John B. Anderson,et al.  Coded Modulation Systems , 2003 .

[14]  K. Takeuchi,et al.  A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[15]  R. Blahut.  Algebraic Codes for Data Transmission , 2002 .

[16]  Yeong-Taek Lee,et al.  A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories , 2008, IEEE Journal of Solid-State Circuits.

[17]  Lee-Fang Wei,et al.  Trellis-coded modulation with multidimensional constellations , 1987, IEEE Trans. Inf. Theory.

[18]  Ken Takeuchi,et al.  A Double-Leve1- V th Select Gate Array Architecture for Multilevel NAND Flash Memories , 1996 .

[19]  John G. Proakis,et al.  Digital Communications , 1983 .

[20]  Yan Li,et al.  A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate , 2009, IEEE Journal of Solid-State Circuits.

[21]  Shu Lin,et al.  Error control coding : fundamentals and applications , 1983 .