A parallel systolic array ASIC for real-time execution of the Hough transform

Many pattern recognition problems can be solved by mapping the input data into an n-dimensional feature space in which a vector indicates a set of attributes. One powerful pattern recognition method is the Hough transform. In reducing the n-dimensional feature space to two dimensions, the coordinate transform can be executed by a systolic array consisting of time-delay processing elements and adders. The application-specific integrated circuit (ASIC) implementation of the Hough transform as a systolic array for real-time recognition of curved tracks in multiwire drift chambers is presented. The array can handle 32 parallel input data streams. It mainly consists of 512 identical programmable processing elements. Sixteen histogram pixels in the feature space are produced in parallel per clock cycle. The ASIC is implemented in 0.6 /spl mu/m CMOS, two-metal layer technology (CUB) from Austria Micro Systems (AMS) and operates with a clock frequency of 100 MHz. The interconnectivity pattern of the processing elements required to initialize the chip according to the pattern recognition task is computed on the host computer using the Hough-transform equations. This pattern is then downloaded to the chip via the data input lines. The Hough-transform ASIC is suitable for a wide range of pattern recognition applications. The integrated circuit is a powerful building block for systems requiring real-time execution of the Hough transform.