A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels

A front-end IC for EPR-IV partial-response maximum likelihood (PRML) detection systems used in magnetic recording systems is developed. Reorganization of the front-end architecture reduces clock acquisition time and lowers chip complexity and power. A new six-pole 80-MHz continuous-time filter equalizes waveforms to the desired ERR-IV target. The equalizer is tuned in quality-factor and frequency to a synthesized system clock, reducing drifts due to processing and temperature variations. An on-chip timing recovery circuit, incorporating a 160-MHz sampled-analog phase detector and 200-MHz voltage-controlled oscillator (VCO) regenerates the data clock. The phase detector used is appropriate for (1, 7) code, and can be extended to operate on (0, k) codes. During head seeks, a secondary loop incorporating the VCO locks to the write clock and acquires the anticipated read-clock frequency. All signal paths are serial and fully differential. The chip is fabricated in a 1-/spl mu/m CMOS process.

[1]  Peter Kabal,et al.  Partial-Response Signaling , 1975, IEEE Trans. Commun..

[2]  Benjamin J. Sheahan,et al.  An analog front-end signal processor for a 64 Mb/s PRML hard-disk drive channel , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[3]  David A. Johns,et al.  Continuous-time LMS adaptive recursive filters , 1991 .

[4]  Hisashi Kobayashi,et al.  Application of probabilistic decoding to digital magnetic recording systems , 1971 .

[5]  Robert Andrew Kertis,et al.  A 16 MB/s PRML read/write data channel , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[6]  K. Parsi,et al.  A 200 Mb/s PRML read/write channel IC , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[7]  Asad A. Abidi,et al.  A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage read channels , 1994 .

[8]  G. David Forney,et al.  Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference , 1972, IEEE Trans. Inf. Theory.

[9]  R. L. Galbraith,et al.  Performance evaluation of the disk drive industry's second-generation partial response maximum likelihood data channel , 1993 .

[10]  S. Moore.  A high performance digital read channel for hard disk drives using PRML techniques , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[11]  Sanroku Tsukamoto,et al.  A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI , 1996 .

[12]  Roger Wood.  Turbo-PRML: a compromise EPRML detector , 1993 .

[13]  A.A. Abidi,et al.  A discrete-time analog signal processor for disk read channels , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[14]  F. Dolivo.  Signal processing for high-density digital magnetic recording , 1989, Proceedings. VLSI and Computer Peripherals. COMPEURO 89.

[15]  R. L. Galbraith,et al.  Implementation of PRML in a rigid disk drive , 1991 .

[16]  T. W. Matthews,et al.  An analog CMOS Viterbi detector for digital magnetic recording , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[17]  K. Nagaraj,et al.  A high speed, low power PRML read channel device , 1995 .

[18]  K. Mueller,et al.  Timing Recovery in Digital Synchronous Data Receivers , 1976, IEEE Trans. Commun..

[19]  T. Matsuura,et al.  A 150 Mb/s PRML chip for magnetic disk drives , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[20]  R. R. Spencer,et al.  An analog discrete-time transversal filter in 2.0 mu m CMOS , 1992, [1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers.

[21]  D. Browning,et al.  A 72 Mb/s PRML disk-drive channel chip with an analog sampled-data signal processor , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[22]  A. M. Patel.  A new digital signal processing channel for data storage products , 1991 .

[23]  Bram Nauta,et al.  A 70 MSample/s 110 mW 8 b CMOS folding interpolating A/D Converter , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[24]  Trent Dudley,et al.  A digital read/write channel with EEPR4 detection , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[25]  P. R. Gray,et al.  A 100 MHz A/D interface for PRML magnetic disk read channels , 1994 .

[26]  Roger W. Wood,et al.  Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel , 1986, IEEE Trans. Commun..

[27]  Laurence B. Milstein,et al.  Dynamic threshold implementation of the maximum-likelihood detector for the EPR4 channel , 1991, IEEE Global Telecommunications Conference GLOBECOM '91: Countdown to the New Millennium. Conference Record.

[28]  Robert Andrew Kertis,et al.  A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection , 1993 .

[29]  L. D. Smith,et al.  A 27MHz Mixed Analog/digital Magnetic Recording Channel DSP Using Partial Response Signalling With Maximum Likelihood Detection , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[30]  Wolfgang Schott,et al.  Fast timing recovery for partial-response signaling systems , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[31]  Scott K. Reynolds,et al.  Digital FIR filters for high speed PRML disk read channels , 1995 .

[32]  Bum S. So,et al.  Performance data for a six-sample look-ahead , 1993 .

[33]  H. Shafiee,et al.  Performance comparison of EPRML and peak detection in high density digital magnetic recording , 1993 .

[34]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[35]  D. Kuai,et al.  A 130 Mb/s PRML read/write channel with digital-servo detection , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[36]  Hisashi Kobayashi,et al.  Application of partial-response channel coding to magnetic recording systems , 1970 .

[37]  Asad A. Abidi,et al.  CMOS active filter design at very high frequencies , 1990 .

[38]  A. A. Abidi,et al.  Analog front-end architectures for high-speed PRML magnetic read channels , 1995 .

[39]  Asad A. Abidi,et al.  A I0-bit, 100 MS/s CMOS A/D Converter , 1996, Proceedings of Custom Integrated Circuits Conference.

[40]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .

[41]  Roy D. Cideciyan,et al.  A PRML System for Digital Magnetic Recording , 1992, IEEE J. Sel. Areas Commun..

[42]  W. L. Abbott,et al.  A digital chip with adaptive equalizer for PRML detection in hard-disk drives , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[43]  D. Dalton,et al.  A 200M sample/s 6b flash ADC in 0.6 /spl mu/m CMOS , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.