Improving Delta-I/sub DDQ/-based test methods

This paper is part of our ongoing effort to replace I/sub DDQ/ testing. We analyze the effect of process drifting based on Sematech Project S121 data, and present a simple and efficient way to deal with these phenomena, when using a previously proposed test procedure based on Delta I/sub DDQ/ histograms. We also analyze the different variance sources in the same context. Following this analysis, we propose and validate an innovative strategy for test optimization based on the use of current test vectors (patterns) with a shorter settling time and on the concept of Delta I/sub DDQ/ partitioning. These new results and developments confirm the pertinence of our variance reduction strategy and reveal new possibilities in terms of test optimization targeting either a better test quality or a shorter current test time.

[1]  Kenneth M. Wallquist,et al.  A General Purpose IDDQ Measurement Circuit , 1993 .

[2]  P. Nigh,et al.  An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[3]  Charles F. Hawkins,et al.  Deep Submicron CMOS Current IC Testing: Is There a Future? , 1999, IEEE Des. Test Comput..

[4]  Claude Thibeault.  An histogram based procedure for current testing of active defects , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  Claude Thibeault,et al.  Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[6]  Claude Thibeault.  On the comparison of /spl Delta/I/sub DDQ/ and I/sub DDQ/ testing , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[7]  Claude Thibeault.  Detection and location of faults and defects using digital signal processing , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[8]  Antoni Ferré,et al.  I/sub DDQ/ characterization in submicron CMOS , 1997, Proceedings International Test Conference 1997.

[9]  Kaushik Roy,et al.  Intrinsic leakage in low power deep submicron CMOS ICs , 1997, Proceedings International Test Conference 1997.

[10]  Richard C. Dorf,et al.  Modern Control Systems, 6th Ed. , 1991 .

[11]  Claude Thibeault,et al.  A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[12]  Anthony C. Miller.  I/sub DDQ/ testing in deep submicron integrated circuits , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[13]  D. Bhovsar.  ITC 99 panels , 1999 .

[14]  Anura P. Jayasumana,et al.  Clustering based techniques for I/sub DDQ/ testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[15]  Jerry M. Soden,et al.  High resolution I/sub DDQ/ characterization and testing-practical issues , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[16]  Robert C. Aitken,et al.  Current ratios: a self-scaling technique for production IDDQ testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[17]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[18]  Paiboon Tangyunyong,et al.  Transient power supply voltage (V/sub DDT/) analysis for detecting IC defects , 1997, Proceedings International Test Conference 1997.

[19]  Kenneth M. Butler,et al.  So what is an optimal test mix? A discussion of the SEMATECH methods experiment , 1997, Proceedings International Test Conference 1997.