A New Technique for Leakage Reduction in DSM Technology

Leakage power is the major constant when scale down the technology in nanometer region. In this paper we propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposal we use lector technique in different logics, we introduce two leakage control transistors (a p-type and a n-type) within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this arrangement, one of the LCTs is always “near its cut off voltage” for any input combination. This increases the resistance of the path from Vdd to ground, leading to significant decrease in leakage currents. Saving of power by proposed circuit is Basic Nand Gate 62.13%, Force Stack 91.11%, Sleep Transistor with Low Vth & High Vth 81.12% & 69.59%, with respect to sleepy Keeper 97.46% .

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