Electrical and optical on-chip interconnects in scaled microprocessors

The interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise. On-chip optical interconnect is therefore being considered as a potential substitute for electrical interconnect. Based on predictions of optical device development, electrical and optical interconnects are compared for various design criteria. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect at the 22 nm technology node are approximately one tenth of the chip edge length.

[1]  M. Paniccia,et al.  A high-speed silicon optical modulator based on a metal–oxide–semiconductor capacitor , 2004, Nature.

[2]  L. Eldada,et al.  Advances in polymer integrated optics , 2000, IEEE Journal of Selected Topics in Quantum Electronics.

[3]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[4]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .

[5]  M. Lipson,et al.  Low-power-consumption short-length and high-modulation-depth silicon electrooptic modulator , 2003 .

[6]  F.J. Leonberger,et al.  Optical interconnections for VLSI systems , 1984, Proceedings of the IEEE.

[7]  Guoqing Chen,et al.  Low power repeaters driving RC interconnects with delay and bandwidth constraints , 2004, IEEE International SOC Conference, 2004. Proceedings..

[8]  Eby G. Friedman,et al.  Sensitivity of interconnect delay to on-chip inductance , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[9]  Eby G. Friedman,et al.  A unified design methodology for CMOS tapered buffers , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[11]  J.C. Campbell,et al.  Metal-germanium-metal photodetectors on heteroepitaxial Ge-on-Si with amorphous Ge Schottky barrier enhancement layers , 2004, IEEE Photonics Technology Letters.

[12]  P. Kapur,et al.  Comparisons between electrical and optical interconnects for on-chip signaling , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

[13]  Joe C. Campbell,et al.  Interdigitated Ge p-i-n photodetectors fabricated on a Si substrate using graded SiGe buffer layers , 2002 .

[14]  Eby G. Friedman,et al.  Optimum wire sizing of RLC interconnect with repeaters , 2003, GLSVLSI '03.

[15]  M.J. Kobrinsky,et al.  Comparisons of conventional, 3-D, optical, and RF interconnects for on-chip clock distribution , 2004, IEEE Transactions on Electron Devices.

[16]  Eby G. Friedman,et al.  Repeater design to reduce delay and power in resistive interconnect , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[17]  Pawan Kapur.  Scaling induced performance challenges/limitations of on-chip metal interconnects and comparisons with optical interconnects , 2002 .

[18]  Stanislav V. Averine,et al.  Geometry optimization of interdigitated Schottky-barrier metal–semiconductor–metal photodiode structures , 2001 .

[19]  Kjell O. Jeppson,et al.  CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.