Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution

This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults are the consequence of resistive-open defects that appear more frequently in VDSM technologies. In particular, the study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect them. This is obtained by changing its addressing order with the purpose of producing the maximal number of RES. This modification does not change the complexity of the algorithm and its capability to detect the former target faults.

[1]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .

[2]  Said Hamdioui,et al.  Importance of dynamic faults for new SRAM technologies , 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

[3]  Said Hamdioui,et al.  Testing static and dynamic faults in random access memories , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[4]  Ad J. van de Goor,et al.  Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[5]  J. Otterstedt,et al.  Integration of non-classical faults in standard March tests , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[6]  Marian Marinescu,et al.  Simple and Efficient Algorithms for Functional RAM Testing , 1982, ITC.

[7]  S. Pravossoudovitch,et al.  Defect-oriented dynamic fault models for embedded-SRAMs , 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

[8]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[9]  Zaid Al-Ars,et al.  Functional memory faults: a formal notation and a taxonomy , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[10]  Rosa Rodríguez-Montañés,et al.  Resistance characterization for weak open defects , 2002, IEEE Design & Test of Computers.