A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

A 0.9–5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between −1.6 and −12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66–82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm2.

[1]  Rinaldo Castello,et al.  SAW-less analog front-end receivers for TDD and FDD , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  Howard C. Luong,et al.  A 0.9GHz–5.8GHz SDR receiver front-end with transformer-based current-gain boosting and 81-dB 3rd-order-harmonic rejection ratio , 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

[3]  N. A. Moseley,et al.  Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference , 2009, IEEE Journal of Solid-State Circuits.

[4]  Hossein Hashemi,et al.  A 0.5-to-3 GHz Software-Defined Radio Receiver Using Discrete-Time RF Signal Processing , 2014, IEEE Journal of Solid-State Circuits.

[5]  A. Gnudi,et al.  A 0.83-2.5-GHz continuously tunable quadrature VCO , 2005, IEEE Journal of Solid-State Circuits.

[6]  Robert B. Staszewski,et al.  A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection , 2016, IEEE Journal of Solid-State Circuits.

[7]  Lu Han,et al.  A Single–Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and ${+}$90 dBm IIP2 , 2009, IEEE Journal of Solid-State Circuits.

[8]  Shiyuan Zheng,et al.  A 4.1-to-6.5GHz transformer-coupled CMOS quadrature digitally-controlled oscillator with quantization noise suppression , 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

[9]  Jonathan Borremans,et al.  A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration , 2014, IEEE Journal of Solid-State Circuits.

[10]  Namsoo Kim,et al.  A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[11]  Minjae Lee,et al.  An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[12]  Ahmad Mirzaei,et al.  Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Howard C. Luong,et al.  A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2nd-order noise-shaping TDC and a transformer-coupled QVCO , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

[14]  Jaeyoung Choi,et al.  A CMOS Wideband RF Front-End With Mismatch Calibrated Harmonic Rejection Mixer for Terrestrial Digital TV Tuner Applications , 2010, IEEE Transactions on Microwave Theory and Techniques.

[15]  Pietro Andreani,et al.  A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[16]  Pierluigi Nuzzo,et al.  A 2-mm$^{2}$ 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS , 2009, IEEE Journal of Solid-State Circuits.

[17]  J.C. Leete,et al.  Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct-Conversion Receivers , 2009, IEEE Journal of Solid-State Circuits.

[18]  Hiu Fai Leung,et al.  A 1.2–6.6GHz LNA using transformer feedback for wideband input matching and noise cancellation in 0.13µm CMOS , 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

[19]  Bram Nauta,et al.  Wideband Low Noise Amplifiers Exploiting Thermal Noise Cancellation , 2005 .

[20]  Jonathan Borremans,et al.  A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers , 2011, IEEE Journal of Solid-State Circuits.

[21]  Ahmad Mirzaei,et al.  A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure , 2012, 2012 IEEE International Solid-State Circuits Conference.

[22]  Hao Wu,et al.  A Blocker-Tolerant Inductor-Less Wideband Receiver With Phase and Thermal Noise Cancellation , 2015, IEEE Journal of Solid-State Circuits.

[23]  Joseph Mitola,et al.  The software radio architecture , 1995, IEEE Commun. Mag..

[24]  Y. Palaskas,et al.  A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[25]  H. C. Luong,et al.  Transformer-based current-gain-boost technique for dual-band and wide-band receiver front-ends , 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

[26]  Joseph Mitola,et al.  Cognitive Radio Architecture Evolution , 2009, Proceedings of the IEEE.