A 10-bit 2.5 GS/s low power hybrid subranging flash-SAR ADC for high data rate communication

The growing need for power aware and energy efficient analog-to-digital converters (ADCs) has led to the development of optimized ADC designs. Though several ADCs are designed using isolated platforms, the usage of hybrid combination has noticeably made an impact in achieving this scenario. The proposed work herein is based on a subranging flash and successive-approximation-register ADC design. The isolated architectures have been redesigned and it is seen to be efficient with a power reduction by 40%. The utilization of comparator with a proposed charge sharing circuitry produces a lower input referred offset voltage during the comparison stages by eliminating the need of a extra circuitry. However, this increases the kick-back noise accounting for the sure trade-off. To reduce these effects a sample and hold switch is used at the comparator input voltage during the decision mode to minimize the kick-back noise thereby keeping the non-linearity errors at minimal. Energy efficiency of 64% have been seen compared to the referred design due to the proposed charge sharing circuitry during the evaluation phase. The converter achieves 61-dB SFDR and 46.5-dB SNDR at 2.5 GS/s for input signal frequency of 100 MHz with a power dissipation of 10.5 mW at 1 V supply.

[1]  Mohammad Taherzadeh-Sani,et al.  A 10-bit 110 kS/s 1.16 $\mu\hbox{W}$ SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  B. Noble,et al.  On certain integrals of Lipschitz-Hankel type involving products of bessel functions , 1955, Philosophical Transactions of the Royal Society of London. Series A, Mathematical and Physical Sciences.

[3]  Pedro M. Figueiredo,et al.  Kickback noise reduction techniques for CMOS latched comparators , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Un-Ku Moon,et al.  Digitally synthesized stochastic flash ADC using only standard digital cells , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[5]  Yun Chiu,et al.  A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS , 2017, IEEE Journal of Solid-State Circuits.

[6]  Reza Lotfi,et al.  Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  D. H. Jacobsohn,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[8]  Jae-Won Nam,et al.  An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Israel A. Wagner,et al.  Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[10]  Michael P. Flynn,et al.  A SAR-Assisted Two-Stage Pipeline ADC , 2011, IEEE Journal of Solid-State Circuits.

[11]  Kwang-Ting Cheng,et al.  Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study , 2010, J. Electron. Test..

[12]  Yong-bin Kim,et al.  A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator , 2011, Analog Integrated Circuits and Signal Processing.

[13]  Edgar Sánchez-Sinencio,et al.  An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure , 2014, IEEE Journal of Solid-State Circuits.

[14]  Sandeep Saini,et al.  Design of low power and high speed multiplexer based Thermometer to Gray encoder , 2013, 2013 International Symposium on Intelligent Signal Processing and Communication Systems.

[15]  Lawrence T. Pileggi,et al.  A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI , 2014, IEEE Journal of Solid-State Circuits.

[16]  Degang Chen,et al.  On Chip Signal Generators for Low Overhead ADC BIST , 2012, Journal of Electronic Testing.

[17]  Mohammad Sharifkhani,et al.  A 4-Bit, 1.6 GS/s Low Power Flash ADC, Based on Offset Calibration and Segmentation , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[18]  Samuel Palermo,et al.  A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[19]  Soon-Jyh Chang,et al.  A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Donald Y. C. Lie,et al.  An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[21]  T. Nirschl,et al.  Yield and speed optimization of a latch-type voltage sense amplifier , 2004, IEEE Journal of Solid-State Circuits.

[22]  Yukihiro Fujimoto,et al.  A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture , 1993 .

[23]  Tadahiro Kuroda,et al.  A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[24]  Jong-In Kim,et al.  A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation , 2015, IEEE Journal of Solid-State Circuits.