Dynamic scheduling in RISC architectures

Multithreaded processors support a number of execution contexts, and switch contexts rapidly in order to tolerate highly latent events such as external memory references. Existing multithreaded architectures are implicitly based on the assumption that latency tolerance requires massive parallelism, which must be found from diverse contexts. The authors have carried out a quantitative analysis of the efficiency of multithreaded execution as a function of the number of threads for two important classes of memory systems: conventional off-chip memory and symmetric networks. The results of these analyses show that there are fundamental reasons for the efficiency to grow very rapidly with the number of threads. This, in turn, implies that the original goal of latency tolerance can be achieved with only a limited number of threads; these can typically be drawn from the same referential context and do not therefore require the heavyweight hardware solutions of conventional multithreading. A novel dynamically scheduled RISC architecture, based on this new understanding of the problem is presented.