Neural network based on-chip thermal simulator

With increasing power densities, runtime thermal management is becoming a necessity in today's systems, especially so for highly integrated Multi-Processor Systems-on-Chip (MPSoCs). In this paper, we propose a neural network (NN) based approach to implement an on-chip thermal simulator to aid such runtime management for MPSoCs. The proposed method combines the advantage of approximating the thermal properties of the chip as a linear system with the ease of fully parallel analog implementation of NNs. We perform a case study with the Niagara UltraSPARC Tl MPSoC for real-life applications, benchmarking our results with an accurate higher order Runge-Kutta (RK4) solver, that is employed in tools such as HotSpot. Within a few gate delays, the proposed NN design can simulate temperatures of the MPSoC 500 ms into the future — corresponding to thousands of iterations of the RK4 solver, with a maximum error of 1–2 K.

[1]  Anne-Johan Annema.  Feed-forward neural networks , 1995 .

[2]  Tajana Rosing,et al.  Proactive temperature balancing for low cost thermal management in MPSoCs , 2008, ICCAD 2008.

[3]  Maurizio Valle,et al.  Analog VLSI Implementation of Artificial Neural Networks with Supervised On-Chip Learning , 2002 .

[4]  Stephen P. Boyd,et al.  Temperature-aware processor frequency assignment for MPSoCs using convex optimization , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[5]  Mohammed Ismail,et al.  Analog VLSI Implementation of Neural Systems , 2011, The Kluwer International Series in Engineering and Computer Science.

[6]  Giovanni De Micheli,et al.  Optimal multi-processor SoC thermal simulation via adaptive differential equation solvers , 2009, 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC).

[7]  David Atienza,et al.  Modeling and dynamic management of 3D multicore systems with liquid cooling , 2009, 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC).

[8]  Giovanni De Micheli,et al.  Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures , 2008, Integr..

[9]  Kurt Hornik,et al.  Learning in linear neural networks: a survey , 1995, IEEE Trans. Neural Networks.

[10]  Giovanni De Micheli,et al.  Multicore thermal management with model predictive control , 2009, 2009 European Conference on Circuit Theory and Design.

[11]  Kunle Olukotun,et al.  Niagara: a 32-way multithreaded Sparc processor , 2005, IEEE Micro.

[12]  J. J. Paulos,et al.  Artificial neural networks using MOS analog multipliers , 1990 .

[13]  Margaret Martonosi,et al.  Techniques for Multicore Thermal Management: Classification and New Exploration , 2006, ISCA 2006.

[14]  M.-N. Sabry.  High-precision compact-thermal models , 2005, IEEE Transactions on Components and Packaging Technologies.

[15]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Tajana Simunic,et al.  Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.