Channel width and length dependence in Si nanocrystal memories with ultra-nanoscale channel

The use of nanoscale channel MOSFETs as a candidate for future nonvolatile memory is extensively investigated. The device consists of a wire channel MOSFET with nanometer dimensions on which Si nanocrystals (Si-NCs) are deposited. The memory characteristics as a function of the channel widths for different channel lengths are presented. The channel length dimensions are defined between 100-1000 nm by electron beam lithography and the width dimensions are reduced from a few tens of nanometers down to sub-5 nm by wet etching and thermal oxidation processes. It is found that the controllability of the fabrication process is enhanced as the channel length is reduced to 100 nm. Moreover, memory performances are improved with decreasing channel width due to the bottleneck effect. These results show that the Si-NCs memory is highly scalable in terms of the channel size. In the narrowest channel devices, i.e., in the sub-5-nm range, coulomb-blockade oscillations are obtained due to the ultra-small regions formed in the channel. In such devices, a strong enhancement of the retention characteristics has been found as a result of the quantum mechanical narrow channel effect in the ultra-narrow channel.

[1]  Sandip Tiwari,et al.  Fast and long retention-time nano-crystal memory , 1996 .

[2]  Sandip Tiwari,et al.  A silicon nanocrystals based memory , 1996 .

[3]  T. Hiramoto,et al.  Large Coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFETs formed by slight oxidation process , 2003 .

[4]  T. Hiramoto,et al.  Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's , 2000, IEEE Electron Device Letters.

[5]  Stephen Y. Chou,et al.  Silicon single-electron quantum-dot transistor switch operating at room temperature , 1998 .

[6]  T. Hiramoto,et al.  Large memory window and long charge-retention time in ultranarrow-channel silicon floating-dot memory , 2003 .

[7]  J.J. Lee,et al.  Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[8]  Toshiro Hiramoto,et al.  Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals , 1998 .

[9]  S. Banerjee,et al.  Memory characterization of SiGe quantum dot flash memories with HfO/sub 2/ and SiO/sub 2/ tunneling dielectrics , 2003 .

[10]  G. Ghibaudo,et al.  Single electron effects and structural effects in ultrascaled silicon nanocrystal floating-gate memories , 2004, IEEE Transactions on Nanotechnology.

[11]  Thierry Baron,et al.  Growth of Si nanocrystals on alumina and integration in memory devices , 2003 .

[12]  Kazuo Yano,et al.  Single-electron memory for giga-to-tera bit storage , 1999, Proc. IEEE.

[13]  Dim-Lee Kwong,et al.  Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric , 2003, VLSIT 2003.

[14]  T. Hiramoto,et al.  Effects of ultra-narrow channel on characteristics of MOSFET memory with silicon nanocrystal floating gates , 2002, Digest. International Electron Devices Meeting,.

[15]  Jong-Ho Lee,et al.  Room temperature single electron effects in a Si nano-crystal memory , 1999 .

[16]  T. Hiramoto,et al.  Room-temperature operation of highly functional single-electron transistor logic based on quantum mechanical effect in ultra-small silicon dot , 2003, IEEE International Electron Devices Meeting 2003.