A modular architecture for dynamically reconfigurable middlebox with customized reconfiguration handler

This paper presents a modular architecture for dynamically reconfigurable middlebox with a customized reconfiguration handler. The data plane of this middlebox can be updated remotely at run-time by client to support post-deployment feature extension, customization and optimization. The proposed Reconfiguration Handler can achieve at least 3.19 Gbps of reconfiguration throughput, which reduces the platform service downtime during dynamic partial reconfiguration. In order to reduce the latency and transmission overhead of remote functional update, partial bitstream is compressed before transmission. The application of the proposed architecture is not limited to network processing as data analytics circuitries can be embedded into the data plane for big data applications.

[1]  Stefano Giordano,et al.  From 1G to 10G: code reuse in action , 2013, HPPN '13.

[2]  Carles Ferrer,et al.  AC_ICAP: A Flexible High Speed ICAP Controller , 2015, Int. J. Reconfigurable Comput..

[3]  Axel Jantsch,et al.  Run-time Partial Reconfiguration speed investigation and architectural design space exploration , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[4]  John W. Lockwood,et al.  SRAM Programming SelectMap Interface EC EC VC VC Four Port Switch ccp Error Check VC VC Control Cell Asynchronous LineCardSwitch InterfaceCircuit Interface Processor Synch , 2001 .

[5]  Jean-Luc Gaudiot,et al.  Minimizing the runtime partial reconfiguration overheads in reconfigurable systems , 2011, The Journal of Supercomputing.

[6]  Chia Yee Ooi,et al.  rrBox: A remote dynamically reconfigurable network processing middlebox , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[7]  José L. Núñez-Yáñez,et al.  Dynamic Reconfiguration Optimisation with Streaming Data Decompression , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[8]  Petar Kočović.  Four laws for today and tomorrow , 2008 .

[9]  Kizheppatt Vipin,et al.  A high speed open source controller for FPGA Partial Reconfiguration , 2012, 2012 International Conference on Field-Programmable Technology.

[10]  Fernanda Gusmão de Lima Kastensmidt,et al.  Dynamic partial reconfiguration manager , 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems.

[11]  Lixin Gao,et al.  Reconfigurable Data Planes for Scalable Network Virtualization , 2013, IEEE Transactions on Computers.

[12]  Junjie Liu,et al.  Building a Flexible and Scalable Virtual Hardware Data Plane , 2012, Networking.

[13]  Kizheppatt Vipin,et al.  ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq , 2014, IEEE Embedded Systems Letters.