A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2nd-order noise-shaping TDC and a transformer-coupled QVCO

A 4.1GHz-6.5GHz all-digital fractional-n frequency synthesizer is presented employing a 2nd-order noise-shaping time-to-digital converter (TDC) and an embedded-FIR-filter transformer-coupled quadrature digitally-control oscillator (QDCO). Implemented in a 65nm CMOS, the prototype measures phase noise of -100dBc/Hz in-band and -145dBc/Hz at 20MHz offset from a 4.5GHz carrier while consuming 26mW from 1.2V supply and occupying 1mm2. The IQ phase error is smaller than 1.2°

[1]  K. Muhammad,et al.  All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.

[2]  Enrico Temporiti,et al.  A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques , 2009, IEEE Journal of Solid-State Circuits.

[3]  Pietro Andreani,et al.  A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[4]  Matthew Z. Straayer,et al.  A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  Matthew Z. Straayer,et al.  A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, IEEE Journal of Solid-State Circuits.

[6]  M.Z. Straayer,et al.  A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping , 2009, IEEE Journal of Solid-State Circuits.

[7]  A. Abidi,et al.  A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue , 2007, 2007 IEEE Symposium on VLSI Circuits.

[8]  Ping-Ying Wang,et al.  A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes , 2009, IEEE Journal of Solid-State Circuits.

[9]  Shiyuan Zheng,et al.  A 4.1-to-6.5GHz transformer-coupled CMOS quadrature digitally-controlled oscillator with quantization noise suppression , 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

[10]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.

[11]  Hong-June Park,et al.  A 0.63ps resolution, 11b pipeline TDC in 0.13µm CMOS , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[12]  Fa Foster Dai,et al.  A 12-bit vernier ring time-to-digital converter in 0.13μm CMOS technology , 2009, 2009 Symposium on VLSI Circuits.